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path: root/hw/intc/armv7m_nvic.c
AgeCommit message (Expand)AuthorFilesLines
2023-10-27target/arm: Move feature test functions to their own headerPeter Maydell1-0/+1
2023-07-25arm: spelling fixesMichael Tokarev1-1/+1
2023-02-27hw/intc/armv7m_nvic: Use QOM cast CPU() macroPhilippe Mathieu-Daudé1-3/+3
2023-02-27target/arm: Wrap arm_rebuild_hflags calls with tcg_enabledFabiano Rosas1-7/+13
2023-02-16target/arm: Store CPUARMState::nvic as NVICState*Philippe Mathieu-Daudé1-25/+13
2022-07-18hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held highPeter Maydell1-1/+8
2021-09-01arm: Move system PPB container handling to armv7mPeter Maydell1-141/+4
2021-09-01arm: Move systick device creation from NVIC to ARMv7M objectPeter Maydell1-73/+0
2021-09-01arm: Move M-profile RAS register block into its own devicePeter Maydell1-56/+0
2021-07-27hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NSPeter Maydell1-7/+24
2021-07-27hw/intc/armv7m_nvic: Correct size of ICSR.VECTPENDINGPeter Maydell1-1/+1
2021-07-27hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interruptsPeter Maydell1-5/+4
2021-06-15hw/intc/armv7m_nvic: Remove stale commentPeter Maydell1-6/+0
2021-05-02Do not include cpu.h if it's not really necessaryThomas Huth1-1/+0
2021-01-08hw/intc/armv7m_nvic: Correct handling of CCR.BFHFNMIGNPeter Maydell1-0/+15
2020-12-10hw/intc/armv7m_nvic: Implement read/write for RAS register blockPeter Maydell1-0/+56
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell1-0/+13
2020-12-10hw/intc/armv7m_nvic: Fix "return from inactive handler" checkPeter Maydell1-27/+32
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell1-8/+18
2020-12-10target/arm: Implement v8.1M REVIDR registerPeter Maydell1-0/+5
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell1-1/+8
2020-12-10hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFaultPeter Maydell1-11/+67
2020-10-01hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUsPeter Maydell1-0/+42
2020-10-01target/arm: Move id_pfr0, id_pfr1 into ARMISARegistersPeter Maydell1-2/+2
2020-09-01hw: Remove superfluous breaksLiao Pingfang1-1/+0
2020-08-03hw/intc/armv7m_nvic: Provide default "reset the system" behaviour for SYSRESE...Peter Maydell1-1/+16
2020-07-10error: Eliminate error_propagate() with Coccinelle, part 1Markus Armbruster1-5/+2
2020-07-10qdev: Use returned bool to check for qdev_realize() etc. failureMarkus Armbruster1-4/+2
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 3Markus Armbruster1-4/+3
2020-06-15sysbus: Convert qdev_set_parent_bus() use with Coccinelle, part 1Markus Armbruster1-5/+3
2020-03-12hw/intc/armv7m_nvic: Rebuild hflags on resetPeter Maydell1-0/+6
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson1-10/+10
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell1-4/+4
2020-02-21target/arm: Define an aa32_pmu_8_1 isar feature test functionPeter Maydell1-1/+1
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
2019-10-24target/arm: Rebuild hflags for M-profile NVICRichard Henderson1-9/+13
2019-09-03memory: Access MemoryRegion with endiannessTony Nguyen1-7/+8
2019-09-03hw/intc/armv7m_nic: Access MemoryRegion with MemOpTony Nguyen1-4/+8
2019-08-16Include hw/qdev-properties.h lessMarkus Armbruster1-0/+1
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster1-0/+1
2019-07-04target/arm: v8M: Check state of exception being returned fromPeter Maydell1-1/+13
2019-07-04arm v8M: Forcibly clear negative-priority exceptions on deactivatePeter Maydell1-5/+35
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster1-1/+1
2019-05-24hw/intc/nvic: Use object_initialize_child for correct reference countingPhilippe Mathieu-Daudé1-3/+3
2019-05-23arm: Remove unnecessary includes of hw/arm/arm.hPeter Maydell1-1/+0
2019-05-07hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from resetPeter Maydell1-1/+3
2019-05-07hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0Peter Maydell1-3/+24
2019-05-07hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()Peter Maydell1-2/+7
2019-04-29target/arm: New function armv7m_nvic_set_pending_lazyfp()Peter Maydell1-0/+96
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