aboutsummaryrefslogtreecommitdiff
path: root/hw/intc/arm_gicv3_redist.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-22hw/intc/arm_gicv3: Update ID and feature registers for GICv4Peter Maydell1-1/+1
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_inv_vlpi()Peter Maydell1-2/+5
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vinvall()Peter Maydell1-1/+7
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_mov_vlpi()Peter Maydell1-2/+18
2022-04-22hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handlingPeter Maydell1-8/+1
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_vlpi_pending()Peter Maydell1-2/+21
2022-04-22hw/intc/arm_gicv3_redist: Implement gicv3_redist_process_vlpi()Peter Maydell1-4/+44
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" codePeter Maydell1-19/+30
2022-04-22hw/intc/arm_gicv3_redist: Recalculate hppvlpi on VPENDBASER writesPeter Maydell1-3/+84
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update hpplpi for all LPIs" logicPeter Maydell1-20/+46
2022-04-22hw/intc/arm_gicv3_redist: Factor out "update hpplpi for one LPI" logicPeter Maydell1-27/+47
2022-04-22hw/intc/arm_gicv3_cpuif: Support vLPIsPeter Maydell1-0/+8
2022-04-22hw/intc/arm_gicv3: Implement new GICv4 redistributor registersPeter Maydell1-0/+56
2022-04-22hw/intc/arm_gicv3: Implement GICv4's new redistributor framePeter Maydell1-4/+4
2022-04-22hw/intc/arm_gicv3_its: Implement VINVALLPeter Maydell1-0/+5
2022-04-22hw/intc/arm_gicv3_its: Implement VMOVIPeter Maydell1-0/+10
2022-04-22hw/intc/arm_gicv3_its: Implement INV for virtual interruptsPeter Maydell1-0/+8
2022-04-22hw/intc/arm_gicv3_its: Implement INV command properlyPeter Maydell1-0/+11
2022-04-22hw/intc/arm_gicv3_its: Handle virtual interrupts in process_its_cmd()Peter Maydell1-0/+9
2022-04-22hw/intc/arm_gicv3: Report correct PIDR0 values for ID registersPeter Maydell1-1/+1
2022-01-28hw/intc/arm_gicv3_its: Implement MOVIPeter Maydell1-0/+53
2022-01-28hw/intc/arm_gicv3_its: Implement MOVALLPeter Maydell1-0/+54
2022-01-28hw/intc/arm_gicv3_redist: Remove unnecessary zero checksPeter Maydell1-5/+3
2022-01-20hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERRORPhilippe Mathieu-Daudé1-2/+2
2021-11-26hw/intc/arm_gicv3: Update cached state after LPI state changesPeter Maydell1-4/+10
2021-11-15hw/intc/arm_gicv3: Support multiple redistributor regionsPeter Maydell1-18/+22
2021-09-13hw/intc: GICv3 redistributor ITS processingShashi Mallela1-0/+141
2021-09-13hw/intc: GICv3 ITS Feature enablementShashi Mallela1-3/+9
2021-07-09hw/intc: Improve formatting of MEMTX_ERROR guest error messageRebecca Cran1-2/+2
2019-06-17hw/intc/arm_gicv3: Fix decoding of ID register rangePeter Maydell1-2/+2
2018-06-22hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati1-1/+2
2018-01-11hw/intc/arm_gicv3: Make reserved register addresses RAZ/WIPeter Maydell1-0/+13
2016-07-19arm_gicv3: Add assert()s to tell Coverity that offsets are alignedPeter Maydell1-0/+4
2016-06-20hw/intc/arm_gicv3: Fix compilation with simple trace backendPeter Maydell1-0/+1
2016-06-17hw/intc/arm_gicv3: Implement CPU i/f SGI generation registersPeter Maydell1-0/+40
2016-06-17hw/intc/arm_gicv3: Implement gicv3_set_irq()Peter Maydell1-0/+21
2016-06-17hw/intc/arm_gicv3: Implement GICv3 redistributor registersShlomo Pongratz1-0/+501
generated by cgit v1.1 at 2024-07-20 20:12:38 +0000