riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-11-26	hw/intc/arm_gicv3: Update cached state after LPI state changes	Peter Maydell	1	-4/+10
2021-11-15	hw/intc/arm_gicv3: Support multiple redistributor regions	Peter Maydell	1	-18/+22
2021-09-13	hw/intc: GICv3 redistributor ITS processing	Shashi Mallela	1	-0/+141
2021-09-13	hw/intc: GICv3 ITS Feature enablement	Shashi Mallela	1	-3/+9
2021-07-09	hw/intc: Improve formatting of MEMTX_ERROR guest error message	Rebecca Cran	1	-2/+2
2019-06-17	hw/intc/arm_gicv3: Fix decoding of ID register range	Peter Maydell	1	-2/+2
2018-06-22	hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR	Amol Surati	1	-1/+2
2018-01-11	hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI	Peter Maydell	1	-0/+13
2016-07-19	arm_gicv3: Add assert()s to tell Coverity that offsets are aligned	Peter Maydell	1	-0/+4
2016-06-20	hw/intc/arm_gicv3: Fix compilation with simple trace backend	Peter Maydell	1	-0/+1
2016-06-17	hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers	Peter Maydell	1	-0/+40
2016-06-17	hw/intc/arm_gicv3: Implement gicv3_set_irq()	Peter Maydell	1	-0/+21
2016-06-17	hw/intc/arm_gicv3: Implement GICv3 redistributor registers	Shlomo Pongratz	1	-0/+501