riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-04-22	hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers	Peter Maydell	1	-1/+1
2022-03-07	hw/intc/arm_gicv3: Fix missing spaces in error log messages	Peter Maydell	1	-2/+2
2021-09-13	hw/intc: GICv3 ITS Feature enablement	Shashi Mallela	1	-1/+4
2021-09-01	hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans	Philippe Mathieu-Daudé	1	-95/+106
2021-09-01	hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix	Philippe Mathieu-Daudé	1	-6/+6
2019-06-17	hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1	Peter Maydell	1	-1/+7
2019-06-17	hw/intc/arm_gicv3: Fix decoding of ID register range	Peter Maydell	1	-2/+2
2018-06-22	hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR	Amol Surati	1	-1/+2
2018-01-11	hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI	Peter Maydell	1	-0/+13
2016-06-20	hw/intc/arm_gicv3: Fix compilation with simple trace backend	Peter Maydell	1	-0/+1
2016-06-17	hw/intc/arm_gicv3: Implement gicv3_set_irq()	Peter Maydell	1	-0/+21
2016-06-17	hw/intc/arm_gicv3: Implement GICv3 distributor registers	Shlomo Pongratz	1	-0/+858