riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-12-15	hw/intc/arm_gicv3: Extract gicv3_set_gicv3state from arm_gicv3_cpuif.c	Philippe Mathieu-Daudé	1	-9/+1
2021-12-07	gicv3: fix ICH_MISR's LRENP computation	Damien Hedde	1	-1/+2
2021-11-29	hw/intc/arm_gicv3: fix handling of LPIs in list registers	Peter Maydell	1	-3/+2
2021-11-26	hw/intc/arm_gicv3: Add new gicv3_intid_is_special() function	Peter Maydell	1	-2/+2
2021-09-20	hw/intc: Set GIC maintenance interrupt level to only 0 or 1	Shashi Mallela	1	-2/+3
2021-09-13	hw/intc: GICv3 redistributor ITS processing	Shashi Mallela	1	-2/+5
2021-07-09	hw/intc/arm_gicv3_cpuif: Fix virtual irq number check in icv_[dir\|eoir]_write	Ricardo Koller	1	-2/+2
2021-06-15	hw/intc/arm_gicv3_cpuif: Tolerate spurious EOIR writes	Jean-Philippe Brucker	1	-1/+4
2021-05-25	hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic	Peter Maydell	1	-16/+32
2020-11-02	hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work	Peter Maydell	1	-3/+2
2020-01-17	arm/gicv3: update virtual irq state after IAR register read	Jeff Kubascik	1	-0/+3
2019-08-16	Include hw/irq.h a lot less	Markus Armbruster	1	-0/+1
2019-05-23	hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3	Peter Maydell	1	-2/+2
2019-05-23	hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}	Peter Maydell	1	-1/+1
2018-12-13	target/arm: Introduce arm_hcr_el2_eff	Richard Henderson	1	-10/+11
2018-08-14	target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}	Peter Maydell	1	-9/+10
2018-07-24	hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQ	Peter Maydell	1	-1/+1
2018-05-31	hw/intc/arm_gicv3: Fix APxR<n> register dispatching	Jan Kiszka	1	-6/+6
2018-04-26	target/arm: Fetch GICv3 state directly from CPUARMState	Aaron Lindsay	1	-8/+2
2018-03-23	hw/intc/arm_gicv3: Fix secure-GIC NS ICC_PMR and ICC_RPR accesses	Peter Maydell	1	-3/+3
2017-06-07	arm_gicv3: Fix ICC_BPR1 reset value when EL3 not implemented	Peter Maydell	1	-5/+1
2017-06-02	hw/intc/arm_gicv3_cpuif: Fix priority masking for NS BPR1	Peter Maydell	1	-4/+38
2017-06-02	hw/intc/arm_gicv3_cpuif: Don't let BPR be set below its minimum	Peter Maydell	1	-0/+6
2017-06-02	hw/intc/arm_gicv3_cpuif: Fix reset value for VMCR_EL2.VBPR1	Peter Maydell	1	-1/+1
2017-02-28	target-arm: Add GICv3CPUState in CPUARMState struct	Vijaya Kumar K	1	-0/+8
2017-02-24	tcg: drop global lock during TCG code execution	Jan Kiszka	1	-0/+3
2017-01-27	arm_gicv3: Fix broken logic in ELRSR calculation	Peter Maydell	1	-1/+1
2017-01-20	hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs	Peter Maydell	1	-10/+60
2017-01-20	hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update()	Peter Maydell	1	-0/+49
2017-01-20	hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR	Peter Maydell	1	-0/+220
2017-01-20	hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers	Peter Maydell	1	-3/+232
2017-01-20	hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors	Peter Maydell	1	-0/+239
2017-01-20	hw/intc/arm_gicv3: Add accessors for ICH_ system registers	Peter Maydell	1	-0/+477
2017-01-20	hw/intc/gicv3: Add data fields for virtualization support	Peter Maydell	1	-0/+13
2016-12-27	hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset	Peter Maydell	1	-7/+6
2016-10-17	hw/intc/arm_gicv3: Fix ICC register tracepoints	Peter Maydell	1	-8/+15
2016-06-27	hw/intc/arm_gicv3: Add missing break	Shannon Zhao	1	-0/+2
2016-06-17	hw/intc/arm_gicv3: Add IRQ handling CPU interface registers	Peter Maydell	1	-0/+437
2016-06-17	hw/intc/arm_gicv3: Implement CPU i/f SGI generation registers	Peter Maydell	1	-0/+125
2016-06-17	hw/intc/arm_gicv3: Implement gicv3_cpuif_update()	Peter Maydell	1	-1/+139
2016-06-17	hw/intc/arm_gicv3: Implement GICv3 CPU interface registers	Peter Maydell	1	-0/+646