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path: root/hw/intc/arm_gic.c
AgeCommit message (Expand)AuthorFilesLines
2018-07-16hw/intc/arm_gic: Fix handling of GICD_ITARGETSRPeter Maydell1-2/+4
2018-07-16hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq()Peter Maydell1-1/+15
2018-02-05qdev: use device_class_set_parent_realize/unrealize/reset()Philippe Mathieu-Daudé1-2/+1
2018-01-25hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1Luc MICHEL1-3/+13
2018-01-25hw/intc/arm_gic: Fix group priority computation for group 1 IRQsLuc MICHEL1-1/+2
2018-01-25hw/intc/arm_gic: Fix C_RPR value on idle priorityLuc MICHEL1-0/+5
2018-01-25hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and ...Luc MICHEL1-0/+1
2018-01-11hw/intc/arm_gic: reserved register addresses are RAZ/WIPeter Maydell1-2/+3
2017-07-11ARM: KVM: Enable in-kernel timers with user space gicAlexander Graf1-0/+7
2017-03-09hw/intc/arm_gic: modernise the DPRINTFAlex Bennée1-4/+9
2017-02-28arm: gic: Remove references to NVICMichael Davidsaver1-26/+5
2016-11-07nvic: set pending status for not active interruptsMarcin Krzeminski1-2/+20
2016-06-06hw/intc/gic: RAZ/WI non-sec access to sec interruptsJens Wiklander1-6/+62
2016-05-19hw: explicitly include qemu/log.hPaolo Bonzini1-0/+1
2016-05-16hw/intc/arm_gic: add tracepointsHollis Blanchard1-0/+12
2016-03-22include/qemu/osdep.h: Don't include qapi/error.hMarkus Armbruster1-0/+1
2016-03-04hw/intc/arm_gic.c: Implement GICv2 GICC_DIRPeter Maydell1-1/+44
2016-01-29arm: Clean up includesPeter Maydell1-0/+1
2016-01-21arm_gic: Update ID registers based on revisionAlistair Francis1-5/+30
2015-11-19hw/arm_gic: Correctly restore nested irq priorityFrançois Baldassari1-2/+2
2015-11-10hw/intc/arm_gic: Remove the definition of NUM_CPUWei Huang1-5/+3
2015-09-11maint: remove double semicolons in many filesDaniel P. Berrange1-1/+1
2015-09-08hw/intc/arm_gic: Actually set the active bits for active interruptsPeter Maydell1-0/+2
2015-09-08hw/intc/arm_gic: Drop running_irq and last_active arraysPeter Maydell1-29/+74
2015-09-08hw/intc/arm_gic: Fix handling of GICC_APR<n>, GICC_NSAPR<n> registersPeter Maydell1-2/+112
2015-09-08hw/intc/arm_gic: Running priority is group priority, not full priorityPeter Maydell1-1/+27
2015-08-13hw/arm/gic: Kill code duplicationPavel Fedin1-45/+19
2015-06-15arm_gic: gic_update should always update all coresJohan Karlsson1-1/+1
2015-05-12hw/intc/arm_gic: Add grouping support to gic_update()Peter Maydell1-5/+22
2015-05-12hw/intc/arm_gic: Change behavior of IAR writesFabian Aggeler1-6/+16
2015-05-12hw/intc/arm_gic: Change behavior of EOIR writesFabian Aggeler1-2/+12
2015-05-12hw/intc/arm_gic: Handle grouping for GICC_HPPIRFabian Aggeler1-1/+27
2015-05-12hw/intc/arm_gic: Restrict priority viewFabian Aggeler1-5/+58
2015-05-12hw/intc/arm_gic: Implement Non-secure view of RPRFabian Aggeler1-1/+18
2015-05-12hw/intc/arm_gic: Make ICCICR/GICC_CTLR bankedFabian Aggeler1-4/+47
2015-05-12hw/intc/arm_gic: Make ICCBPR/GICC_BPR bankedFabian Aggeler1-5/+26
2015-05-12hw/intc/arm_gic: Make ICDDCR/GICD_CTLR bankedFabian Aggeler1-5/+23
2015-05-12hw/intc/arm_gic: Add Interrupt Group RegistersFabian Aggeler1-3/+47
2015-05-12hw/intc/arm_gic: Switch to read/write callbacks with tx attributesPeter Maydell1-54/+90
2015-05-12hw/intc/arm_gic: Add Security Extensions propertyFabian Aggeler1-1/+4
2015-05-12hw/intc/arm_gic: Create outbound FIQ linesFabian Aggeler1-0/+3
2015-03-19Fix remaining warnings from Sparse (void return)Stefan Weil1-1/+2
2014-10-24arm_gic: remove unused parameter.KONRAD Frederic1-2/+2
2014-08-29hw/intc/arm_gic: honor target mask in gic_update()Sergey Fedorov1-1/+2
2014-08-29arm_gic: Do not force PPIs to edge-triggered modeAdam Lackorzynski1-1/+1
2014-08-29arm_gic: GICD_ICFGR: Write model only for pre v1 GICsAdam Lackorzynski1-4/+6
2014-08-29arm_gic: Fix read of GICD_ICFGRAdam Lackorzynski1-1/+1
2014-05-05arm: Clean up fragile use of error_is_set() in realize() methodsMarkus Armbruster1-2/+4
2014-02-20hw/intc/arm_gic: Fix NVIC assertion failurePeter Maydell1-1/+1
2014-02-08arm_gic: Add GICC_APRn state to the GICStateChristoffer Dall1-0/+5
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