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7 daysi386/tdx: Build TDX only for 64-bit targetXiaoyao Li1-1/+1
Build errors related to TDX were reported when QEMU built on 32-bit host[1][2]. Since TDX cannot work on 32-bit host and it's also not worth supporting TDX with 32-bit QEMU, limit TDX to 64-bit target only. [1] https://lore.kernel.org/qemu-devel/20250602173101.1052983-1-clg@redhat.com/ [2] https://lore.kernel.org/qemu-devel/b8171c39-6a92-4078-a59a-a63d7452e1e9@kaod.org/ Suggested-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Tested-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250625073310.2796298-1-xiaoyao.li@intel.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-06-03i386/tdvf: Fix build on 32-bit hostCédric Le Goater1-3/+3
Use PRI formats where required. Cc: Isaku Yamahata <isaku.yamahata@intel.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/r/20250602173101.1052983-3-clg@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-06-02Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi2-10/+15
into staging virtio,pci,pc: features, fixes, tests vhost will now no longer set a call notifier if unused some work towards loongarch testing based on bios-tables-test some core pci work for SVM support in vtd vhost vdpa init has been optimized for response time to QMP A couple more fixes Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCgAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmg97ZUPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpRBsH/0Fx4NNMaynXmVOgV1rMFirTydhQG5NSdeJv # i1RHd25Rne/RXH0CL71UPuOPADWh6bv9iZTg6RU6g7TwI8K9v3M0R71RlPLh1Lh1 # x7fifWNSNXVi18fM9/j+mIg7I2Ye0AaqveezRJWGzqoOxQKKlVI2xspKZBCCkygd # i2tgtR1ORB6+ji6wVoTDPlL42X5Jef5MUT3XOcRR5biHm0JfqxxQKVM83mD+5yMI # 0YqjT2BVRzo5rGN7mSuf7tQ50xI6I0wI1+eoWeKHRbg08f709M8TZRDKuVh24Evg # 9WnIhKLTzRVdCNLNbw9h9EhxoANpWCyvmnn6GCfkJui40necFHY= # =0lO6 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 02 Jun 2025 14:29:41 EDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (26 commits) hw/i386/pc_piix: Fix RTC ISA IRQ wiring of isapc machine vdpa: move memory listener register to vhost_vdpa_init vdpa: move iova_tree allocation to net_vhost_vdpa_init vdpa: reorder listener assignment vdpa: add listener_registered vdpa: set backend capabilities at vhost_vdpa_init vdpa: reorder vhost_vdpa_set_backend_cap vdpa: check for iova tree initialized at net_client_start vhost: Don't set vring call if guest notifier is unused tests/qtest/bios-tables-test: Use MiB macro rather hardcode value tests/data/uefi-boot-images: Add ISO image for LoongArch system uefi-test-tools:: Add LoongArch64 support pci: Add a PCI-level API for PRI pci: Add a pci-level API for ATS pci: Add a pci-level initialization function for IOMMU notifiers memory: Store user data pointer in the IOMMU notifiers pci: Add an API to get IOMMU's min page size and virtual address width pci: Cache the bus mastering status in the device pcie: Helper functions to check to check if PRI is enabled pcie: Add a helper to declare the PRI capability for a pcie device ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-06-02hw/i386/pc_piix: Fix RTC ISA IRQ wiring of isapc machineBernhard Beschow1-0/+5
Commit 56b1f50e3c10 ("hw/i386/pc: Wire RTC ISA IRQs in south bridges") attempted to refactor RTC IRQ wiring which was previously done in pc_basic_device_init() but forgot about the isapc machine. Fix this by wiring in the code section dedicated exclusively to the isapc machine. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2961 Fixes: 56b1f50e3c10 ("hw/i386/pc: Wire RTC ISA IRQs in south bridges") cc: qemu-stable Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Message-Id: <20250526203820.1853-1-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-06-01hw/i386/amd_iommu: Fix xtsup when vcpus < 255Vasant Hegde1-0/+8
If vCPUs > 255 then x86 common code (x86_cpus_init()) call kvm_enable_x2apic(). But if vCPUs <= 255 then the common code won't calls kvm_enable_x2apic(). This is because commit 8c6619f3e692 ("hw/i386/amd_iommu: Simplify non-KVM checks on XTSup feature") removed the call to kvm_enable_x2apic when xtsup is "on", which break things when guest is booted with x2apic mode and there are <= 255 vCPUs. Fix this by adding back kvm_enable_x2apic() call when xtsup=on. Fixes: 8c6619f3e692 ("hw/i386/amd_iommu: Simplify non-KVM checks on XTSup feature") Reported-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Tested-by: Tested-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com> Message-Id: <20250516100535.4980-3-sarunkod@amd.com> Fixes: 8c6619f3e692 ("hw/i386/amd_iommu: Simplify non-KVM checks on XTSup feature") Reported-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Tested-by: Tested-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Joao Martins <joao.m.martins@oracle.com> Signed-off-by: Vasant Hegde <vasant.hegde@amd.com> Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
2025-06-01hw/i386/amd_iommu: Fix device setup failure when PT is on.Sairaj Kodilkar1-10/+2
Commit c1f46999ef506 ("amd_iommu: Add support for pass though mode") introduces the support for "pt" flag by enabling nodma memory when "pt=off". This allowed VFIO devices to successfully register notifiers by using nodma region. But, This also broke things when guest is booted with the iommu=nopt because, devices bypass the IOMMU and use untranslated addresses (IOVA) to perform DMA reads/writes to the nodma memory region, ultimately resulting in a failure to setup the devices in the guest. Fix the above issue by always enabling the amdvi_dev_as->iommu memory region. But this will once again cause VFIO devices to fail while registering the notifiers with AMD IOMMU memory region. Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode") Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> Message-Id: <20250516100535.4980-2-sarunkod@amd.com> Fixes: c1f46999ef506 ("amd_iommu: Add support for pass though mode") Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com> Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
2025-05-30Merge tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi4-89/+6
staging * Functional tests improvements * Endianness improvements/clean-ups for the Microblaze machines * Remove obsolete -2.4 and -2.5 i440fx and q35 machine types and related code # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmg5mlARHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbX1eRAAjvTK4noIfzc9QQI7EyUafgdp65m44wwx # vfjlLbhmEnWFF11Qhovc6o36N4zF4Pt30mbXZs0gQaDR5H9RT8wrg9kShirhZX3O # 4raPHCJFBviUCktSg90eFtvuQnfVK9cBMB8PMRQix+V5wRXcCx+cc6ebnQZ+UHp4 # L2d+qKRoHCPRO/dvQth4Be7a5pXqFQeu4gq7i/w9PCa7O+akSM3lc8dsJPuCiXgQ # R7dkwsrRQzmiEC6aDmauNpsRRs0yptQs+9b83V4moLX07hk/R/I59EDFQqALLim7 # jmSbLnulKSSCeatV54PE/K4QxT62iA2OuJ6wo/vzVBGpzLdKE4aq99OcNPDxwWi0 # wc6xVDNtMyr81Ex4pZ0WgVKt57tDBIp9RijB5wTAhRPqKgnHtRGVNqX9TrsFls5L # jIyKgfTxFKf9RA/a53p3uUXNmpLDVG63AhA9jWrAUtGOGJ0V+cDD2hTygXai8XTS # 66aiEdMiuPFV2fApaEftcySFrMoT7RG1JHlcMjsTOpRdZF/x+rehFQKOHcdBeJ6r # /zJ18MXbd5vEcglBz8joPwHu3mt2NLew+IvLPoAlwMfrniiNnUC+IY2Jzz3jYpBI # WbbaesVG7J8SzJ6SwNOVuiCbiAImOkrxEz/8Jm783sZvWSzLYmwI9bBp9KXVxGty # ed14fLi8g5U= # =8SJJ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 30 May 2025 07:45:20 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-05-30' of https://gitlab.com/thuth/qemu: (25 commits) tests/unit/test-util-sockets: fix mem-leak on error object hw/net/vmxnet3: Merge DeviceRealize in InstanceInit hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_DISABLE_PCIE definition hw/net/vmxnet3: Remove VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS definition hw/scsi/vmw_pvscsi: Convert DeviceRealize -> InstanceInit hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_DISABLE_PCIE_BIT definition hw/scsi/vmw_pvscsi: Remove PVSCSI_COMPAT_OLD_PCI_CONFIGURATION definition hw/core/machine: Remove hw_compat_2_5[] array hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDE hw/i386/x86: Remove X86MachineClass::save_tsc_khz field hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machines hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_DISABLE_PCIE definition hw/virtio/virtio-pci: Remove VIRTIO_PCI_FLAG_MIGRATE_EXTRA definition hw/net/e1000: Remove unused E1000_FLAG_MAC flag hw/core/machine: Remove hw_compat_2_4[] array hw/i386/pc: Remove pc_compat_2_4[] array hw/i386/pc: Remove PCMachineClass::broken_reserved_end field hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machines docs: Deprecate the qemu-system-microblazeel binary hw/microblaze: Remove the big-endian variants of ml605 and xlnx-zynqmp-pmu ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi9-14/+385
* target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-05-30hw/nvram/fw_cfg: Remove legacy FW_CFG_ORDER_OVERRIDEPhilippe Mathieu-Daudé1-6/+1
The MachineClass::legacy_fw_cfg_order boolean was only used by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got removed. Remove it along with: - FW_CFG_ORDER_OVERRIDE_* definitions - fw_cfg_set_order_override() - fw_cfg_reset_order_override() - fw_cfg_order[] - rom_set_order_override() - rom_reset_order_override() Simplify CLI and pc_vga_init() / pc_nic_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-12-philmd@linaro.org> [thuth: Fix error from check_patch.pl wrt to an empty "for" loop] Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/x86: Remove X86MachineClass::save_tsc_khz fieldPhilippe Mathieu-Daudé1-1/+0
The X86MachineClass::save_tsc_khz boolean was only used by the pc-q35-2.5 and pc-i440fx-2.5 machines, which got removed. Remove it and simplify tsc_khz_needed(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-11-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove deprecated pc-q35-2.5 and pc-i440fx-2.5 machinesPhilippe Mathieu-Daudé3-29/+0
These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed. Remove the now unused empty pc_compat_2_5[] array. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-10-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove pc_compat_2_4[] arrayPhilippe Mathieu-Daudé1-19/+0
The pc_compat_2_4[] array was only used by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed. Remove it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-4-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove PCMachineClass::broken_reserved_end fieldPhilippe Mathieu-Daudé1-8/+5
The PCMachineClass::broken_reserved_end field was only used by the pc-q35-2.4 and pc-i440fx-2.4 machines, which got removed. Remove it and simplify pc_memory_init(). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-3-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-30hw/i386/pc: Remove deprecated pc-q35-2.4 and pc-i440fx-2.4 machinesPhilippe Mathieu-Daudé2-26/+0
These machines has been supported for a period of more than 6 years. According to our versioned machine support policy (see commit ce80c4fa6ff "docs: document special exception for machine type deprecation & removal") they can now be removed. Remove the qtest in test-x86-cpuid-compat.c file. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Message-ID: <20250512083948.39294-2-philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-05-28i386/apic: Skip kvm_apic_put() for TDXXiaoyao Li1-0/+5
KVM neithers allow writing to MSR_IA32_APICBASE for TDs, nor allow for KVM_SET_LAPIC[*]. Note, KVM_GET_LAPIC is also disallowed for TDX. It is called in the path do_kvm_cpu_synchronize_state() -> kvm_arch_get_registers() -> kvm_get_apic() and it's already disllowed for confidential guest through guest_state_protected. [*] https://lore.kernel.org/all/Z3w4Ku4Jq0CrtXne@google.com/ Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-42-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdx: Setup the TD HOB listXiaoyao Li3-1/+157
The TD HOB list is used to pass the information from VMM to TDVF. The TD HOB must include PHIT HOB and Resource Descriptor HOB. More details can be found in TDVF specification and PI specification. Build the TD HOB in TDX's machine_init_done callback. Co-developed-by: Isaku Yamahata <isaku.yamahata@intel.com> Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-24-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdx: Track mem_ptr for each firmware entry of TDVFXiaoyao Li1-0/+1
For each TDVF sections, QEMU needs to copy the content to guest private memory via KVM API (KVM_TDX_INIT_MEM_REGION). Introduce a field @mem_ptr for TdxFirmwareEntry to track the memory pointer of each TDVF sections. So that QEMU can add/copy them to guest private memory later. TDVF sections can be classified into two groups: - Firmware itself, e.g., TDVF BFV and CFV, that located separately from guest RAM. Its memory pointer is the bios pointer. - Sections located at guest RAM, e.g., TEMP_MEM and TD_HOB. mmap a new memory range for them. Register a machine_init_done callback to do the stuff. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-21-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdx: Don't initialize pc.rom for TDX VMsXiaoyao Li1-13/+16
For TDX, the address below 1MB are entirely general RAM. No need to initialize pc.rom memory region for TDs. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-20-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdx: Parse TDVF metadata for TDX VMXiaoyao Li1-0/+7
After TDVF is loaded to bios MemoryRegion, it needs parse TDVF metadata. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-19-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdvf: Introduce function to parse TDVF metadataIsaku Yamahata3-0/+190
TDX VM needs to boot with its specialized firmware, Trusted Domain Virtual Firmware (TDVF). QEMU needs to parse TDVF and map it in TD guest memory prior to running the TDX VM. A TDVF Metadata in TDVF image describes the structure of firmware. QEMU refers to it to setup memory for TDVF. Introduce function tdvf_parse_metadata() to parse the metadata from TDVF image and store the info of each TDVF section. TDX metadata is located by a TDX metadata offset block, which is a GUID-ed structure. The data portion of the GUID structure contains only an 4-byte field that is the offset of TDX metadata to the end of firmware file. Select X86_FW_OVMF when TDX is enable to leverage existing functions to parse and search OVMF's GUID-ed structures. Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com> Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-18-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386/tdx: load TDVF for TD guestChao Peng1-1/+5
TDVF(OVMF) needs to run at private memory for TD guest. TDX cannot support pflash device since it doesn't support read-only private memory. Thus load TDVF(OVMF) with -bios option for TDs. Use memory_region_init_ram_guest_memfd() to allocate the MemoryRegion for TDVF because it needs to be located at private memory. Also store the MemoryRegion pointer of TDVF since the shared ramblock of it can be discared after it gets copied to private ramblock. Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Co-developed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-17-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28i386: Introduce tdx-guest objectXiaoyao Li1-0/+5
Introduce tdx-guest object which inherits X86_CONFIDENTIAL_GUEST, and will be used to create TDX VMs (TDs) by qemu -machine ...,confidential-guest-support=tdx0 \ -object tdx-guest,id=tdx0 It has one QAPI member 'attributes' defined, which allows user to set TD's attributes directly. Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250508150002.689633-3-xiaoyao.li@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-28qapi: make Xen event commands unconditionally availableDaniel P. Berrangé2-14/+1
This removes the TARGET_I386 condition from the Xen event channel commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-7-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: make SGX commands unconditionally availableDaniel P. Berrangé2-2/+2
This removes the TARGET_I386 condition from the SGX confidential virtualization commands, moving them to the recently introduced misc-i386.json QAPI file, given they are inherantly i386 specific commands. Observe a pre-existing bug that the "SGXEPCSection" struct lacked a TARGET_I386 condition, despite its only usage being behind a TARGET_I386 condition. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-6-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-28qapi: expose rtc-reset-reinjection command unconditionallyDaniel P. Berrangé1-1/+1
This removes the TARGET_I386 condition from the rtc-reset-reinjection command. This requires providing a QMP command stub for non-i386 target. This in turn requires moving the command out of misc-target.json, since that will trigger symbol poisoning errors when built from target independent code. Rather than putting the command into misc.json, it is proposed to create misc-$TARGET.json files to hold commands whose impl is conceptually only applicable to a single target. This gives an obvious docs hint to consumers that the command is only useful in relation a specific target, while misc.json is for commands applicable to 2 or more targets. The current impl of qmp_rtc_reset_reinject() is a no-op if the i386 RTC is disabled in Kconfig, or if the running machine type lack any RTC device. The stub impl for non-i386 targets retains this no-op behaviour. However, it is now reporting an Error mentioning this command is not available for current target. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-ID: <20250522190542.588267-2-pierrick.bouvier@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2025-05-20qapi/misc-target: Rename SGXInfo to SgxInfoZhao Liu2-9/+9
QAPI requires strict PascalCase naming style, i.e., only the first letter of a single word is allowed to be uppercase, which could help with readability. Rename SGXInfo to SgxInfo. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250516091130.2374221-3-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-20qapi/misc-target: Rename SGXEPCSection to SgxEpcSectionZhao Liu1-9/+9
QAPI requires strict PascalCase naming style, i.e., only the first letter of a single word is allowed to be uppercase, which could help with readability. Rename SGXEPCSection to SgxEpcSection. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Link: https://lore.kernel.org/r/20250516091130.2374221-2-zhao1.liu@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-05-14hw/i386/amd_iommu: Allow migration when explicitly create the AMDVI-PCI deviceSuravee Suthikulpanit2-1/+49
Add migration support for AMD IOMMU model by saving necessary AMDVIState parameters for MMIO registers, device table, command buffer, and event buffers. Also change devtab_len type from size_t to uint64_t to avoid 32-bit build issue. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Message-Id: <20250504170405.12623-3-suravee.suthikulpanit@amd.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14hw/i386/amd_iommu: Isolate AMDVI-PCI from amd-iommu device to allow full ↵Suravee Suthikulpanit3-26/+38
control over the PCI device creation Current amd-iommu model internally creates an AMDVI-PCI device. Here is a snippet from info qtree: bus: main-system-bus type System dev: amd-iommu, id "" xtsup = false pci-id = "" intremap = "on" device-iotlb = false pt = true ... dev: q35-pcihost, id "" MCFG = -1 (0xffffffffffffffff) pci-hole64-size = 34359738368 (32 GiB) below-4g-mem-size = 134217728 (128 MiB) above-4g-mem-size = 0 (0 B) smm-ranges = true x-pci-hole64-fix = true x-config-reg-migration-enabled = true bypass-iommu = false bus: pcie.0 type PCIE dev: AMDVI-PCI, id "" addr = 01.0 romfile = "" romsize = 4294967295 (0xffffffff) rombar = -1 (0xffffffffffffffff) multifunction = false x-pcie-lnksta-dllla = true x-pcie-extcap-init = true failover_pair_id = "" acpi-index = 0 (0x0) x-pcie-err-unc-mask = true x-pcie-ari-nextfn-1 = false x-max-bounce-buffer-size = 4096 (4 KiB) x-pcie-ext-tag = true busnr = 0 (0x0) class Class 0806, addr 00:01.0, pci id 1022:0000 (sub 1af4:1100) ... This prohibits users from specifying the PCI topology for the amd-iommu device, which becomes a problem when trying to support VM migration since it does not guarantee the same enumeration of AMD IOMMU device. Therefore, allow the 'AMDVI-PCI' device to optionally be pre-created and associated with a 'amd-iommu' device via a new 'pci-id' parameter on the latter. For example: -device AMDVI-PCI,id=iommupci0,bus=pcie.0,addr=0x05 \ -device amd-iommu,intremap=on,pt=on,xtsup=on,pci-id=iommupci0 \ For backward-compatibility, internally create the AMDVI-PCI device if not specified on the CLI. Co-developed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Message-Id: <20250504170405.12623-2-suravee.suthikulpanit@amd.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14intel_iommu: Take locks when looking for and creating address spacesCLEMENT MATHIEU--DRIF1-1/+24
vtd_find_add_as can be called by multiple threads which leads to a race condition. Taking the IOMMU lock ensures we avoid such a race. Moreover we also need to take the bql to avoid an assert to fail in memory_region_add_subregion_overlap when actually allocating a new address space. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250430124750.240412-3-clement.mathieu--drif@eviden.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-14intel_iommu: Use BQL_LOCK_GUARD to manage cleanup automaticallyCLEMENT MATHIEU--DRIF1-9/+1
vtd_switch_address_space needs to take the BQL if not already held. Use BQL_LOCK_GUARD to make the iommu implementation more consistent. Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@eviden.com> Message-Id: <20250430124750.240412-2-clement.mathieu--drif@eviden.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-05-08hw/i386/acpi-build: Fix typo and grammar in commentGustavo Romero1-1/+1
Fix typo and verb conjugation in a comment about FADT initialization. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-ID: <20250504215639.54860-7-gustavo.romero@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-05-08hw/i386/acpi-build: Update document referenceGustavo Romero1-1/+1
Update the reference for QEMU's ACPI PCI hotplug device interface. Also, use the possessive form in the comment. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-ID: <20250504215639.54860-9-gustavo.romero@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-05-08hw/i386/acpi-build: Fix build_append_notfication_callback typoEric Auger1-4/+4
Rename build_append_notfication_callback into build_append_notification_callback Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Message-ID: <20250428102628.378046-4-eric.auger@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-25qom: Make InterfaceInfo[] uses constPhilippe Mathieu-Daudé7-7/+7
Mechanical change using: $ sed -i -E 's/\(InterfaceInfo.?\[/\(const InterfaceInfo\[/g' \ $(git grep -lE '\(InterfaceInfo.?\[\]\)') Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20250424194905.82506-7-philmd@linaro.org>
2025-04-25qom: Have class_init() take a const data argumentPhilippe Mathieu-Daudé26-29/+30
Mechanical change using gsed, then style manually adapted to pass checkpatch.pl script. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250424194905.82506-4-philmd@linaro.org>
2025-04-24Merge tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi4-8/+1
Miscellaneous patches for 2025-04-24 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmgJ7dYSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTiZIP/1PFAg/s3SoiLQwH/ZrjyUkm1kiKnjOH # CC5Stw6I9tuYnDAhASAdSymofLv0NNydNe5ai6ZZAWRyRYjIcfNigKAGK4Di+Uhe # nYxT0Yk8hNGwMhl6NnBp4mmCUNCwcbjT9uXdiYQxFYO/qqYR1388xJjeN3c362l3 # AaLrE5bX5sqa6TAkTeRPjeIqxlyGT7jnCrN7I1hMhDvbc3ITF3AMfYFMjnmAQgr+ # mTWGS1QogqqkloODbR1DKD1CAWOlpK+0HibhNF+lz71P0HlwVvy+HPXso505Wf0B # dMwlSrZ1DnqNVF/y5IhMEMslahKajbjbFVhBjmrGl/8T821etCxxgB20c0vyFRy8 # qTyJGwBZaEo0VWr70unSmq45TRoeQvdHAw/e+GtilR0ci80q2ly4gbObnw7L8le+ # gqZo4IWmrwp2sbPepE57sYKQpEndwbRayf/kcFd0LPPpeINu9ZooXkYX0pOo6Cdg # vDKMaEB1/fmPhjSlknxkKN9LZdR+nDw8162S1CKsUdWanAOjmP8haN19aoHhIekZ # q+r2qUq/U827yNy9/qbInmsoFYDz9s6sAOE63jibd5rZZ9Anei6NOSgLzA4CqCR1 # +d0+TXp19gP9mLMFs7/ZclwkXCz47OQYhXYphjI3wM9x+xbdRcI4n+DOH5u5coKx # AsA6+2n0GF4Y # =GaoH # -----END PGP SIGNATURE----- # gpg: Signature made Thu 24 Apr 2025 03:52:54 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-misc-2025-04-24' of https://repo.or.cz/qemu/armbru: cleanup: Drop pointless label at end of function cleanup: Drop pointless return at end of function cleanup: Re-run return_directly.cocci Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-04-24cleanup: Drop pointless return at end of functionMarkus Armbruster3-5/+0
A few functions now end with a label. The next commit will clean them up. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250407082643.2310002-3-armbru@redhat.com> [Straightforward conflict with commit 988ad4ccebb6 (hw/loongarch/virt: Fix cpuslot::cpu set at last in virt_cpu_plug()) resolved]
2025-04-24cleanup: Re-run return_directly.cocciMarkus Armbruster1-3/+1
Coccinelle's indentation of virt_create_plic() results in a long line. Avoid that by mimicking the old indentation manually. Don't touch tests/tcg/mips/user/. I'm not sure these files are ours to make style cleanups on. They might be imported third-party code, which we should leave as is to not complicate future updates. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250407082643.2310002-2-armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-23exec/cpu-all: remove exec/target_page includePierrick Bouvier4-0/+4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/system: Move exec/address-spaces.h to system/address-spaces.hRichard Henderson6-6/+6
Convert the existing includes with sed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/system: Move exec/memory.h to system/memory.hRichard Henderson3-3/+3
Convert the existing includes with sed -i ,exec/memory.h,system/memory.h,g Move the include within cpu-all.h into a !CONFIG_USER_ONLY block. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23hw: add compat machines for 10.1Cornelia Huck3-4/+25
Add 10.1 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Message-ID: <20250414094543.221241-1-cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-04-02hw/i386/amd_iommu: Assign pci-id 0x1419 for the AMD IOMMU deviceSuravee Suthikulpanit1-0/+1
Currently, the QEMU-emulated AMD IOMMU device use PCI vendor id 0x1022 (AMD) with device id zero (undefined). Eventhough this does not cause any functional issue for AMD IOMMU driver since it normally uses information in the ACPI IVRS table to probe and initialize the device per recommendation in the AMD IOMMU specification, the device id zero causes the Windows Device Manager utility to show the device as an unknown device. Since Windows only recognizes AMD IOMMU device with device id 0x1419 as listed in the machine.inf file, modify the QEMU AMD IOMMU model to use the id 0x1419 to avoid the issue. This advertise the IOMMU as the AMD IOMMU device for Family 15h (Models 10h-1fh). Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Message-Id: <20250325021140.5676-1-suravee.suthikulpanit@amd.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Yan Vugenfirer <yvugenfi@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2025-03-20rust: Kconfig: Factor out whether HPET is Rust or CPeter Maydell2-2/+2
Currently we require everywhere that wants to know if there is an HPET device to check for "CONFIG_HPET || CONFIG_X_HPET_RUST". Factor out whether the HPET device is Rust or C into a separate Kconfig stanza, so that CONFIG_HPET means "there is an HPET", and whether this has pulled in CONFIG_X_HPET_RUST or CONFIG_HPET_C is something the rest of QEMU can ignore. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Link: https://lore.kernel.org/r/20250319193110.1565578-3-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-11hw/i386/fw_cfg: Check ACPI availability with acpi_builtin()Philippe Mathieu-Daudé1-4/+4
Define acpi_tables / acpi_tables_len stubs, then replace the compile-time CONFIG_ACPI check in fw_cfg.c by a runtime one. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20250307223949.54040-4-philmd@linaro.org>
2025-03-05Merge tag 'hw-misc-20250305' of https://github.com/philmd/qemu into stagingStefan Hajnoczi2-0/+7
Misc HW patches - Remove TCG dependency on ARM_GICV3 (Philippe) - Add MMIO interface to PVPanic device (Alexander) - Add vmapple machine (Alexander & Phil) - Restrict part of sPAPR PAGE_INIT hypercall to TCG (Philippe) - Make ghes_record_cper_errors() scope static (Gavin) - Do not expose the ARM virt machines on Xen-only binary (Philippe) - Xen header cleanups (Philippe) - Set Freescale eTSEC network device description & category (Zoltan) - Improve RX FIFO depth for various UARTs (Philippe) - Prevent TX FIFO memory leak in SiFive UART (Alistair) - Cleanups in MacIO and AT24C EEPROM (Zoltan) - Add UFS temperature event notification support & test (Keoseong) - Remove printf() calls in hw/arm/ (Peter) # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmfHpagACgkQ4+MsLN6t # wN4dTg//Z2neoENdnZglRp6q66LLxSTHJnHUMNHe2Bp+KKfhce+//j+CFYgOnJjV # P5eExzvHvtYFL6lNXOR7MTM/i/4pixcLYh8anyrnUWkEiufGXI4/30QePbwAAdkZ # kQ1CpLI43ZdnMLTh18JswLo/JMkl/jJGvCGNjhtQVnobqam+ATgAbjmcnwA8esJS # cCQVFzno9TNvsCnUtMe3IdOfIs9K3atCARbXpA3i3wd52P+NHvGO1jU0QPFBm2Lr # 4kcFLI1Sg2vYWD3FujDPeCcfI7kcRDIjHS6vVplK1VlCjjdaQmxx6XKO72PnZZOG # 7sra8xJpW8mZS2jfN2AxKMVlNndZMYzAJoS2UBMp1YX8KBEzlcmI2uSjGas6bcmQ # XIaP7/mggx7yBU3nspUl8rqY/3Z3wVjwepf1l8KOn9Z13wo+APv4aj6W+zkK96A5 # NGq6EpoKquINGLBBMkZAdfBOKk97NhwHh1Op04VgJNnPESpLnb5hENtZW1ksg92r # tijWdDWnC/JtWMU2dAnmT/9Vaxk4fukGqqncXqQJzGBw0OylzWh5b2Zer02WFyxz # oplISEwU3uFcg0OLa9aUHgs7lVWBUbEW3pSk1CtKuqgPtwxm/Gr2KbAVgAbFiyzr # 6YPQsfFP5z6CjreOWMELPWmsYV+jtTj/KoIek2QlYt7Ex6uiA6c= # =TcY9 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 05 Mar 2025 09:15:20 HKT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'hw-misc-20250305' of https://github.com/philmd/qemu: (41 commits) hw/nvram/eeprom_at24c: Reorganise init to avoid overwriting values hw/nvram/eeprom_at24c: Remove memset after g_malloc0 hw/nvram/eeprom_at24c: Remove ERR macro that calls fprintf to stderr hw/nvram/eeprom_at24c: Use OBJECT_DECLARE_SIMPLE_TYPE hw/arm/versatilepb: Convert printfs to LOG_GUEST_ERROR hw/arm/omap_sx1: Remove ifdeffed out debug printf hw/arm/omap1: Convert information printfs to tracepoints hw/arm/omap1: Drop ALMDEBUG ifdeffed out code hw/arm/omap1: Convert raw printfs to qemu_log_mask() tests/qtest/ufs-test: Add test code for the temperature feature hw/ufs: Add temperature event notification support hw/misc/macio/gpio: Add constants for register bits hw/misc/macio: Improve trace logs hw/char/sifive_uart: Free fifo on unrealize hw/char/sh_serial: Return correct number of empty RX FIFO elements hw/char/mcf_uart: Really use RX FIFO depth hw/char/mcf_uart: Use FIFO_DEPTH definition instead of magic values hw/char/imx_serial: Really use RX FIFO depth hw/char/bcm2835_aux: Really use RX FIFO depth hw/char/pl011: Really use RX FIFO depth ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-03-04hw/xen/xen-hvm: Reduce included headersPhilippe Mathieu-Daudé1-0/+6
Have "hw/xen/xen-hvm-common.h" include the bare minimal set of headers. Adapt sources to avoid errors when refactoring unrelated headers such: include/hw/xen/xen-hvm-common.h:71:5: error: unknown type name ‘xenevtchn_handle’ 71 | xenevtchn_handle *xce_handle; | ^~~~~~~~~~~~~~~~ hw/xen/xen-hvm-common.c: In function ‘cpu_get_ioreq’: hw/xen/xen-hvm-common.c:227:13: error: implicit declaration of function ‘hw_error’ 227 | hw_error("Fatal error while trying to get io event!\n"); | ^~~~~~~~ | herror hw/xen/xen-hvm-common.c: In function ‘handle_ioreq’: hw/xen/xen-hvm-common.c:446:34: error: ‘target_ulong’ undeclared (first use in this function) 446 | (req->size < sizeof (target_ulong))) { | ^~~~~~~~~~~~ hw/i386/xen/xen-hvm.c: In function ‘xen_add_to_physmap’: hw/i386/xen/xen-hvm.c:298:22: error: implicit declaration of function ‘xen_replace_cache_entry’ 298 | uint8_t *p = xen_replace_cache_entry(phys_offset, start_addr, size); | ^~~~~~~~~~~~~~~~~~~~~~~ hw/i386/xen/xen-hvm.c:314:9: error: implicit declaration of function 'error_report' is invalid in C99 314 | error_report("relocate_memory %lu pages from GFN %"HWADDR_PRIx ^~~~~~~~~~~~ hw/i386/xen/xen-hvm.c: In function ‘xen_log_global_start’: hw/i386/xen/xen-hvm.c:465:9: error: implicit declaration of function ‘xen_enabled’ 465 | if (xen_enabled()) { | ^~~~~~~~~~~ hw/i386/xen/xen-hvm.c: In function ‘regs_to_cpu’: hw/i386/xen/xen-hvm.c:487:5: error: unknown type name ‘X86CPU’ 487 | X86CPU *cpu; | ^~~~~~ hw/i386/xen/xen-hvm.c:492:15: error: ‘R_EAX’ undeclared (first use in this function) 492 | env->regs[R_EAX] = req->data; | ^~~~~ | REG_RAX Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Message-Id: <20250218162618.46167-6-philmd@linaro.org>
2025-03-04hw/xen/xen-pvh: Reduce included headersPhilippe Mathieu-Daudé1-0/+1
Have "hw/xen/xen-pvh-common.h" include the bare minimal set of headers. Adapt sources to avoid errors when refactoring unrelated headers such: hw/i386/xen/xen-pvh.c: In function ‘xen_pvh_machine_class_init’: hw/i386/xen/xen-pvh.c:84:28: error: ‘TARGET_DEFAULT_CPU_TYPE’ undeclared (first use in this function) 84 | mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; | ^~~~~~~~~~~~~~~~~~~~~~~ hw/xen/xen-pvh-common.c: In function ‘xen_pvh_init’: hw/xen/xen-pvh-common.c:217:43: error: ‘MiB’ undeclared (first use in this function) 217 | if (s->cfg.pci_ecam.size != 256 * MiB) { | ^~~ hw/xen/xen-hvm-common.c:18:6: error: no previous prototype for ‘xen_mr_is_memory’ [-Werror=missing-prototypes] 18 | bool xen_mr_is_memory(MemoryRegion *mr) | ^~~~~~~~~~~~~~~~ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-Id: <20250218162618.46167-5-philmd@linaro.org>
2025-03-04hw/uefi-vars-sysbus: allow for pc and q35Gerd Hoffmann2-0/+4
Allow the device being added to x86_64 pc and q35 VMs. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20250225163031.1409078-23-kraxel@redhat.com>
generated by cgit v1.1 at 2025-07-10 16:38:37 +0000