riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-01-18	intel-iommu: Extend address width to 48 bits	Prasad Singamsetty	1	-6/+3
2018-01-18	intel-iommu: Redefine macros to enable supporting 48 bit address width	Prasad Singamsetty	1	-8/+26
2017-08-02	intel_iommu: fix iova for pt	Peter Xu	1	-1/+0
2017-06-16	intel_iommu: cleanup vtd_{do_}iommu_translate()	Peter Xu	1	-0/+1
2017-05-25	intel_iommu: support passthrough (PT)	Peter Xu	1	-0/+1
2017-04-20	intel_iommu: enable remote IOTLB	Peter Xu	1	-0/+1
2017-02-17	intel_iommu: add "caching-mode" option	Aviv Ben-David	1	-0/+1
2017-01-10	intel_iommu: support device iotlb descriptor	Jason Wang	1	-2/+11
2016-11-15	intel_iommu: fixing source id during IOTLB hash key calculation	Jason Wang	1	-1/+1
2016-07-21	intel_iommu: support all masks in interrupt entry cache invalidation	Radim Krčmář	1	-0/+1
2016-07-21	intel_iommu: Add support for Extended Interrupt Mode	Jan Kiszka	1	-0/+2
2016-07-21	x86-iommu: introduce IEC notifiers	Peter Xu	1	-4/+20
2016-07-20	intel_iommu: Add support for PCI MSI remap	Peter Xu	1	-0/+2
2016-07-20	intel_iommu: add IR translation faults defines	Peter Xu	1	-0/+13
2016-07-20	intel_iommu: define interrupt remap table addr register	Peter Xu	1	-0/+4
2016-07-20	intel_iommu: set IR bit for ECAP register	Peter Xu	1	-0/+2
2016-07-20	intel_iommu: allow queued invalidation for IR	Peter Xu	1	-0/+2
2016-02-06	intel_iommu: large page support	Jason Wang	1	-2/+4
2014-08-28	intel-iommu: add IOTLB using hash table	Le Tan	1	-1/+33
2014-08-28	intel-iommu: add context-cache to cache context-entry	Le Tan	1	-7/+16
2014-08-28	intel-iommu: add supports for queued invalidation interface	Le Tan	1	-6/+21
2014-08-28	intel-iommu: introduce Intel IOMMU (VT-d) emulation	Le Tan	1	-0/+333