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path: root/hw/i2c/aspeed_i2c.c
AgeCommit message (Expand)AuthorFilesLines
2024-09-16hw/i2c/aspeed: Add support for 64 bit addressesJamin Lin1-0/+14
2024-09-16hw/i2c/aspeed: Add support for Tx/Rx buffer 64 bit addressesJamin Lin1-0/+48
2024-09-16hw/i2c/aspeed: Add AST2700 supportJamin Lin1-0/+62
2024-09-16hw/i2c/aspeed: Introduce a new dma_dram_offset attribute in AspeedI2CbusJamin Lin1-19/+32
2024-09-16hw/i2c/aspeed: Support discontinuous poll buffer memory region of I2C busJamin Lin1-1/+2
2024-09-16hw/i2c/aspeed: Introduce a new bus pool buffer attribute in AspeedI2CbusJamin Lin1-18/+113
2024-09-16hw/i2c/aspeed: Support discontinuous register memory region of I2C busJamin Lin1-1/+2
2024-09-13hw: Use device_class_set_legacy_reset() instead of opencodingPeter Maydell1-2/+2
2024-07-21hw/i2c/aspeed: rename the I2C class pool attribute to share_poolJamin Lin1-18/+21
2024-07-21hw/i2c/aspeed: support to set the different memory sizeJamin Lin1-1/+5
2023-12-29hw/i2c: Constify VMStateRichard Henderson1-2/+2
2023-09-29aspeed/i2c: Clean up local variable shadowingCédric Le Goater1-1/+0
2023-09-01hw/i2c/aspeed: Add support for buffer organizationHang Yu1-0/+4
2023-09-01hw/i2c/aspeed: Fix TXBUF transmission start position errorHang Yu1-24/+6
2023-09-01hw/i2c/aspeed: Fix Tx count and Rx size error in buffer pool modeHang Yu1-4/+4
2023-03-02hw/i2c: only schedule pending master when bus is idleKlaus Jensen1-0/+2
2022-10-24hw/i2c/aspeed: Fix old reg slave receivePeter Delevoryas1-3/+5
2022-06-30hw/i2c/aspeed: Add new-registers DMA slave mode RX supportPeter Delevoryas1-12/+121
2022-06-30hw/i2c/aspeed: add slave device in old register modeKlaus Jensen1-9/+80
2022-06-30hw/i2c/aspeed: Fix MASTER_EN missing error messagePeter Delevoryas1-2/+2
2022-06-30hw/i2c/aspeed: Fix DMA len write-enable bit handlingPeter Delevoryas1-4/+4
2022-06-30hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL referencePeter Delevoryas1-1/+1
2022-06-30aspeed/i2c: Change trace event for NORMAL_STOP statesCédric Le Goater1-1/+1
2022-06-22aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH alwaysCédric Le Goater1-3/+10
2022-06-22hw/i2c/aspeed: add DEV_ADDR in old register modeKlaus Jensen1-2/+2
2022-06-22hw/i2c/aspeed: rework raise interrupt trace eventKlaus Jensen1-12/+22
2022-06-22aspeed/i2c: Add ast1030 controller modelsCédric Le Goater1-0/+24
2022-06-22aspeed: i2c: Move regs and helpers to header fileJoe Komlodi1-266/+0
2022-06-22aspeed: i2c: Add PKT_DONE IRQ to traceJoe Komlodi1-0/+3
2022-06-22aspeed: i2c: Add new mode supportJoe Komlodi1-194/+650
2022-06-22aspeed: i2c: Use reg array instead of individual varsJoe Komlodi1-155/+126
2022-06-22aspeed: i2c: Migrate to registerfields APIJoe Komlodi1-197/+196
2021-10-12aspeed/i2c: QOMify AspeedI2CBusCédric Le Goater1-18/+83
2021-05-01aspeed/i2c: Rename DMA address spaceCédric Le Goater1-1/+2
2021-05-01aspeed/i2c: Fix DMA address maskCédric Le Goater1-1/+1
2020-07-16hw/i2c/aspeed_i2c: Simplify aspeed_i2c_get_bus()Philippe Mathieu-Daudé1-2/+1
2020-02-06aspeed/i2c: Prevent uninitialized warningMiroslav Rezanina1-1/+1
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau1-1/+1
2019-12-16aspeed/i2c: Add trace eventsCédric Le Goater1-13/+80
2019-12-16aspeed/i2c: Add support for DMA transfersCédric Le Goater1-3/+123
2019-12-16aspeed/i2c: Check SRAM enablement on AST2500Cédric Le Goater1-0/+37
2019-12-16aspeed/i2c: Add support for pool buffer transfersCédric Le Goater1-19/+178
2019-10-15aspeed/i2c: Add AST2600 supportCédric Le Goater1-2/+44
2019-10-15aspeed/i2c: Introduce an object class per SoCCédric Le Goater1-8/+52
2019-08-16Include migration/vmstate.h lessMarkus Armbruster1-0/+1
2019-08-16Include hw/irq.h a lot lessMarkus Armbruster1-0/+1
2019-06-12Include qemu/module.h where needed, drop it from qemu-common.hMarkus Armbruster1-0/+1
2019-02-27i2c: Don't check return value from i2c_recv()Corey Minyard1-7/+2
2018-09-25aspeed/i2c: Fix receive done interrupt handlingGuenter Roeck1-1/+9
2018-09-25aspeed/i2c: Handle receive command in separate functionGuenter Roeck1-16/+21
generated by cgit v1.1 at 2024-11-20 17:42:39 +0000