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7 dayshw/char/bcm2835_aux: Fix incorrect interrupt ID when RX disabledChung-Yi Chen1-1/+1
Fix a misconfiguration issue in the read implementation of the AUX_MU_IIR_REG register. This issue can lead to a transmit interrupt being incorrectly interpreted as a receive interrupt when the receive interrupt is disabled and the receive FIFO holds valid bytes. The AUX_MU_IIR_REG register (interrupt ID bits [2:1]) indicates the status of mini UART interrupts: - 00: No interrupts - 01: Transmit FIFO is empty - 10: Receive FIFO is not empty - 11: <Not possible> When the transmit interrupt is enabled and the receive interrupt is disabled, the original code incorrectly sets the interrupt ID bits. Specifically: 1. Transmit FIFO empty, receive FIFO empty - Expected 0b01, returned 0b01 (correct) 2. Transmit FIFO empty, receive FIFO not empty - Expected 0b01, returned 0b10 (incorrect) In the second case, the code sets the interrupt ID to 0b10 (receive FIFO is not empty) even if the receive interrupt is disabled. To fix this, the patch adds additional condition for setting the interrupt ID bits to also check if the receive interrupt is enabled. Reference: BCM2835 ARM Peripherals, page 13. Available on https://datasheets.raspberrypi.com/bcm2835/bcm2835-peripherals.pdf Fixes: 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX (aka UART1) block") Signed-off-by: Chung-Yi Chen <yeechen0207@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20250328123725.94176-1-yeechen0207@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-20rust: Kconfig: Factor out whether PL011 is Rust or CPeter Maydell2-1/+7
Currently every board that uses the PL011 duplicates the logic that selects the Rust implementation if Rust was enabled and the C implementation if it does not. Factor this out into a separate Kconfig stanza, so that boards can go back to simply doing "select PL011" and get whichever implementation is correct for the build. This fixes a compilation failure if CONFIG_VMAPPLE is enabled in a Rust build, because hw/vmapple/Kconfig didn't have the "pick the Rust PL011 if Rust is enabled" logic in it. Fixes: 59f4d65584bd33 ("hw/vmapple/vmapple: Add vmapple machine type") Reported-by: Tanish Desai <tanishdesai37@gmail.com> Analyzed-by: Tanish Desai <tanishdesai37@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20250319193110.1565578-2-peter.maydell@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-03-14Revert "hw/char/pl011: Warn when using disabled receiver"Paolo Bonzini1-9/+10
The guest does not control whether characters are sent on the UART. Sending them before the guest happens to boot will now result in a "guest error" log entry that is only because of timing, even if the guest _would_ later setup the receiver correctly. This reverts the bulk of commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df, and instead adds a comment about why we don't check the enable bits. Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20250311153717.206129-1-pbonzini@redhat.com [PMM: expanded comment] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-03-04hw/char/sifive_uart: Free fifo on unrealizeAlistair Francis1-16/+28
We previously allocate the fifo on reset and never free it, which means we are leaking memory. Instead let's allocate on realize and free on unrealize. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Clément Chigot <chigot@adacore.com> Message-ID: <20250303023120.157221-1-alistair.francis@wdc.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-04hw/char/sh_serial: Return correct number of empty RX FIFO elementsPhilippe Mathieu-Daudé1-16/+14
In the IOCanReadHandler sh_serial_can_receive(), if the Serial Control Register 'Receive Enable' bit is set (bit 4), then we return a size of (1 << 4) which happens to be equal to 16, so effectively SH_RX_FIFO_LENGTH. The IOReadHandler, sh_serial_receive1() takes care to receive multiple chars, but if the FIFO is partly filled, we only process the number of free slots in the FIFO, discarding the other chars! Fix by returning how many elements the FIFO can queue in the IOCanReadHandler, so we don't have to process more than that in the IOReadHandler, thus not discarding anything. Remove the now unnecessary check on 's->rx_cnt < SH_RX_FIFO_LENGTH' in IOReadHandler, reducing the block indentation. Fixes: 63242a007a1 ("SH4: Serial controller improvement") Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-10-philmd@linaro.org>
2025-03-04hw/char/mcf_uart: Really use RX FIFO depthPhilippe Mathieu-Daudé1-2/+4
While we model a 4-elements RX FIFO since the MCF UART model was introduced in commit 20dcee94833 ("MCF5208 emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Tested-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-9-philmd@linaro.org>
2025-03-04hw/char/mcf_uart: Use FIFO_DEPTH definition instead of magic valuesPhilippe Mathieu-Daudé1-3/+7
Defines FIFO_DEPTH and use it, fixing coding style. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Thomas Huth <huth@tuxfamily.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-8-philmd@linaro.org>
2025-03-04hw/char/imx_serial: Really use RX FIFO depthPhilippe Mathieu-Daudé1-2/+6
While we model a 32-elements RX FIFO since the IMX serial model was introduced in commit 988f2442971 ("hw/char/imx_serial: Implement receive FIFO and ageing timer") we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20250220092903.3726-7-philmd@linaro.org>
2025-03-04hw/char/bcm2835_aux: Really use RX FIFO depthPhilippe Mathieu-Daudé1-2/+4
While we model a 8-elements RX FIFO since the BCM2835 AUX model was introduced in commit 97398d900ca ("bcm2835_aux: add emulation of BCM2835 AUX block") we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-6-philmd@linaro.org>
2025-03-04hw/char/pl011: Really use RX FIFO depthPhilippe Mathieu-Daudé1-3/+5
While we model a 16-elements RX FIFO since the PL011 model was introduced in commit cdbdb648b7c ("ARM Versatile Platform Baseboard emulation"), we only read 1 char at a time! Have the IOCanReadHandler handler return how many elements are available, and use that in the IOReadHandler handler. Example of FIFO better used by enabling the pl011 tracing events and running the tests/functional/test_aarch64_virt.py tests: pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_receive recv 5 chars pl011_fifo_rx_put RX FIFO push char [0x72] 1/16 depth used pl011_irq_state irq state 1 pl011_fifo_rx_put RX FIFO push char [0x6f] 2/16 depth used pl011_fifo_rx_put RX FIFO push char [0x6f] 3/16 depth used pl011_fifo_rx_put RX FIFO push char [0x74] 4/16 depth used pl011_fifo_rx_put RX FIFO push char [0x0d] 5/16 depth used pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_write addr 0x038 value 0x00000050 reg IMSC pl011_irq_state irq state 1 pl011_can_receive LCR 0x70, RX FIFO used 5/16, can_receive 11 chars pl011_read addr 0x03c value 0x00000030 reg RIS pl011_write addr 0x044 value 0x00000000 reg ICR pl011_irq_state irq state 1 pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 4/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x00000072 reg DR pl011_can_receive LCR 0x70, RX FIFO used 4/16, can_receive 12 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 3/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x0000006f reg DR pl011_can_receive LCR 0x70, RX FIFO used 3/16, can_receive 13 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 2/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x0000006f reg DR pl011_can_receive LCR 0x70, RX FIFO used 2/16, can_receive 14 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 1/16 pl011_irq_state irq state 1 pl011_read addr 0x000 value 0x00000074 reg DR pl011_can_receive LCR 0x70, RX FIFO used 1/16, can_receive 15 chars pl011_read addr 0x018 value 0x00000080 reg FR pl011_read_fifo RX FIFO read, used 0/16 pl011_irq_state irq state 0 pl011_read addr 0x000 value 0x0000000d reg DR pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_read addr 0x018 value 0x00000090 reg FR pl011_read addr 0x03c value 0x00000020 reg RIS pl011_write addr 0x038 value 0x00000050 reg IMSC pl011_irq_state irq state 0 pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_can_receive LCR 0x70, RX FIFO used 0/16, can_receive 16 chars pl011_read addr 0x018 value 0x00000090 reg FR pl011_write addr 0x000 value 0x00000072 reg DR Inspired-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-5-philmd@linaro.org>
2025-03-04hw/char/pl011: Improve RX flow tracing eventsPhilippe Mathieu-Daudé2-7/+10
Log FIFO use (availability and depth). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-4-philmd@linaro.org>
2025-03-04hw/char/pl011: Simplify a bit pl011_can_receive()Philippe Mathieu-Daudé1-2/+3
Introduce 'fifo_depth' and 'fifo_available' local variables to better express the 'r' variable use. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250220092903.3726-3-philmd@linaro.org>
2025-03-04hw/char/pl011: Warn when using disabled receiverPhilippe Mathieu-Daudé1-0/+9
We shouldn't receive characters when the full UART or its receiver is disabled. However we don't want to break the possibly incomplete "my first bare metal assembly program"s, so we choose to simply display a warning when this occurs. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Luc Michel <luc.michel@amd.com> Message-Id: <20250220092903.3726-2-philmd@linaro.org>
2025-02-16hw/char/xilinx_uartlite: Make device endianness configurablePhilippe Mathieu-Daudé1-11/+23
Replace the DEVICE_NATIVE_ENDIAN MemoryRegionOps by a pair of DEVICE_LITTLE_ENDIAN / DEVICE_BIG_ENDIAN. Add the "endianness" property to select the device endianness. This property is unspecified by default, and machines need to set it explicitly. Set the proper endianness for each machine using the device. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250213122217.62654-6-philmd@linaro.org>
2025-02-04hw/char: Add emulation of Diva GSP PCI management boardsHelge Deller3-0/+301
The Diva GSP ("Guardian Service Processor") PCI boards are Remote Management cards for PA-RISC machines. They come with built-in 16550A UARTs for serial consoles and modem functionalities, as well as a mailbox-like memory area for hardware auto-reboot functionality. Latest generation HP PA-RISC server machines use those Diva cards for console output. Signed-off-by: Helge Deller <deller@gmx.de>
2025-01-31hw/char/pci-multi: Convert legacy qemu_allocate_irqs to qemu_init_irqPhilippe Mathieu-Daudé1-4/+3
There are a fixed number of PCI IRQs, known beforehand. Allocate them within PCIMultiSerialState, and initialize using qemu_init_irq(), allowing to remove the legacy qemu_allocate_irqs() and qemu_free_irqs() calls. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121182828.45088-1-philmd@linaro.org>
2025-01-31hw/ipack: Remove legacy qemu_allocate_irqs() usePhilippe Mathieu-Daudé1-2/+2
No need to dynamically allocate IRQ when we know before hands how many we'll use. Declare the 2 of them in IPackDevice state and initialize them in the DeviceRealize handler. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250121155526.29982-4-philmd@linaro.org>
2025-01-31hw/ipack: Clarify KConfig symbolsPhilippe Mathieu-Daudé2-1/+6
Split IPACK Kconfig key as {IPACK, TPCI200, IP_OCTAL_232} - IPack is a bus - TPCI200 is a PCI device providing an IPack bus - IP-Octal232 is an IPack device plugged on an IPack bus Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Fabiano Rosas <farosas@suse.de> Message-Id: <20250121155526.29982-3-philmd@linaro.org>
2025-01-27hw/char/imx_serial: Update all state before restarting ageing timerBernhard Beschow1-3/+3
Fixes characters to be "echoed" after each keystroke rather than after every other since imx_serial_rx_fifo_ageing_timer_restart() would see ~UTS1_RXEMPTY only after every other keystroke. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-27hw/char/imx_serial: Fix reset value of UFCR registerBernhard Beschow1-0/+1
The value of the UCFR register is respected when echoing characters to the terminal, but its reset value is reserved. Fix the reset value to the one documented in the datasheet. While at it move the related attribute out of the section of unimplemented registers since its value is actually respected. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-19hw/char/riscv_htif: Convert HTIF_DEBUG() to trace eventsPhilippe Mathieu-Daudé2-12/+7
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250116223609.81594-1-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2025-01-15hw/xen: Fix errp handling in xen_consoleDavid Woodhouse1-13/+21
When attempting to read the 'output' node, interpret any error *other* than ENOENT as a fatal error. For ENOENT, fall back to serial_hd() to find a character device, or create a null device. Do not attempt to prepend to errp when serial_hd() fails; the error isn't relevant (and prior to this change, wasn't set anyway). Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
2025-01-15hw/xen: Use xs_node_read() from xen_console_get_name()David Woodhouse1-9/+9
Now that xs_node_read() can construct a node path, no need to open-code it. Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Acked-by: Roger Pau Monné <roger.pau@citrix.com>
2025-01-15xen: do not use '%ms' scanf specifierRoger Pau Monne1-2/+4
The 'm' parameter used to request auto-allocation of the destination variable is not supported on FreeBSD, and as such leads to failures to parse. What's more, the current usage of '%ms' with xs_node_scanf() is pointless, as it just leads to a double allocation of the same string. Instead use xs_node_read() to read the whole xenstore node. Fixes: a783f8ad4ec9 ('xen: add a mechanism to automatically create XenDevice-s...') Fixes: 9b7737469080 ('hw/xen: update Xen console to XenDevice model') Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Signed-off-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
2025-01-13hw/char/imx_serial: Turn some DPRINTF() statements into trace eventsBernhard Beschow2-19/+44
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250111183711.2338-9-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-01-13hw/char/stm32f2xx_usart: replace print with traceNikita Shubin2-26/+29
Drop debug printing macros and replace them with according trace functions. Signed-off-by: Nikita Shubin <n.shubin@yadro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241220111756.16511-1-nikita.shubin@maquefel.me> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-12-21Merge tag 'exec-20241220' of https://github.com/philmd/qemu into stagingStefan Hajnoczi7-11/+11
Accel & Exec patch queue - Ignore writes to CNTP_CTL_EL0 on HVF ARM (Alexander) - Add '-d invalid_mem' logging option (Zoltan) - Create QOM containers explicitly (Peter) - Rename sysemu/ -> system/ (Philippe) - Re-orderning of include/exec/ headers (Philippe) Move a lot of declarations from these legacy mixed bag headers: . "exec/cpu-all.h" . "exec/cpu-common.h" . "exec/cpu-defs.h" . "exec/exec-all.h" . "exec/translate-all" to these more specific ones: . "exec/page-protection.h" . "exec/translation-block.h" . "user/cpu_loop.h" . "user/guest-host.h" . "user/page-protection.h" # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmdlnyAACgkQ4+MsLN6t # wN6mBw//QFWi7CrU+bb8KMM53kOU9C507tjn99LLGFb5or73/umDsw6eo/b8DHBt # KIwGLgATel42oojKfNKavtAzLK5rOrywpboPDpa3SNeF1onW+99NGJ52LQUqIX6K # A6bS0fPdGG9ZzEuPpbjDXlp++0yhDcdSgZsS42fEsT7Dyj5gzJYlqpqhiXGqpsn8 # 4Y0UMxSL21K3HEexlzw2hsoOBFA3tUm2ujNDhNkt8QASr85yQVLCypABJnuoe/// # 5Ojl5wTBeDwhANET0rhwHK8eIYaNboiM9fHopJYhvyw1bz6yAu9jQwzF/MrL3s/r # xa4OBHBy5mq2hQV9Shcl3UfCQdk/vDaYaWpgzJGX8stgMGYfnfej1SIl8haJIfcl # VMX8/jEFdYbjhO4AeGRYcBzWjEJymkDJZoiSWp2NuEDi6jqIW+7yW1q0Rnlg9lay # ShAqLK5Pv4zUw3t0Jy3qv9KSW8sbs6PQxtzXjk8p97rTf76BJ2pF8sv1tVzmsidP # 9L92Hv5O34IqzBu2oATOUZYJk89YGmTIUSLkpT7asJZpBLwNM2qLp5jO00WVU0Sd # +kAn324guYPkko/TVnjC/AY7CMu55EOtD9NU35k3mUAnxXT9oDUeL4NlYtfgrJx6 # x1Nzr2FkS68+wlPAFKNSSU5lTjsjNaFM0bIJ4LCNtenJVP+SnRo= # =cjz8 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 20 Dec 2024 11:45:20 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'exec-20241220' of https://github.com/philmd/qemu: (59 commits) util/qemu-timer: fix indentation meson: Do not define CONFIG_DEVICES on user emulation system/accel-ops: Remove unnecessary 'exec/cpu-common.h' header system/numa: Remove unnecessary 'exec/cpu-common.h' header hw/xen: Remove unnecessary 'exec/cpu-common.h' header target/mips: Drop left-over comment about Jazz machine target/mips: Remove tswap() calls in semihosting uhi_fstat_cb() target/xtensa: Remove tswap() calls in semihosting simcall() helper accel/tcg: Un-inline translator_is_same_page() accel/tcg: Include missing 'exec/translation-block.h' header accel/tcg: Move tcg_cflags_has/set() to 'exec/translation-block.h' accel/tcg: Restrict curr_cflags() declaration to 'internal-common.h' qemu/coroutine: Include missing 'qemu/atomic.h' header exec/translation-block: Include missing 'qemu/atomic.h' header accel/tcg: Declare cpu_loop_exit_requested() in 'exec/cpu-common.h' exec/cpu-all: Include 'cpu.h' earlier so MMU_USER_IDX is always defined target/sparc: Move sparc_restore_state_to_opc() to cpu.c target/sparc: Uninline cpu_get_tb_cpu_state() target/loongarch: Declare loongarch_cpu_dump_state() locally user: Move various declarations out of 'exec/exec-all.h' ... Conflicts: hw/char/riscv_htif.c hw/intc/riscv_aplic.c target/s390x/cpu.c Apply sysemu header path changes to not in the pull request. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-21Merge tag 'pull-riscv-to-apply-20241220' of ↵Stefan Hajnoczi1-5/+10
https://github.com/alistair23/qemu into staging RISC-V PR for 10.0 * Correct the validness check of iova * Fix APLIC in_clrip and clripnum write emulation * Support riscv-iommu-sys device * Add Tenstorrent Ascalon CPU * Add AIA userspace irqchip_split support * Add Microblaze V generic board * Upgrade ACPI SPCR table to support SPCR table revision 4 format * Remove tswap64() calls from HTIF * Support 64-bit address of initrd * Introduce svukte ISA extension * Support ssstateen extension * Support for RV64 Xiangshan Nanhu CPU # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmdkzjgACgkQr3yVEwxT # gBOcyA//e0XhAQciQglCZZCfINdOyI8qSh+P2K0qtrXZ4VERHEMp7UoD5CQr2cZv # h8ij1EkatXCwukVELx0rNckxG33bEFgG1oESnQSrwGE0Iu4csNW24nK5WlUS0/r+ # A5oD2wtzEF+cbhTKrVSDBN/PvlnWTKGEoJRkuXWfz5d4uR9eyQhfED0S2j36lNEC # X1x/OZoKM89XuXtOFe9g55Z5UNzAatcdTISozL0FydiPh7QeVjTLHh28/tt559MX # 7v5aJFlQuZ78z1mIHkZmPSorSrJ0zqhkP6NWe1ae06oMgzwRQQhYLppDILV4ZgUF # 3mSDRoXmBycQXiYNPcHep3LdXfvxr+PpWHSevx8gH1jwm93On7Y/H7Uol6TDXzfC # mrFjalfV5tzrD90ZvB+s5bCMF1q5Z8Dlj0pYF9aN9P1ILoWy3dndFAPJB6uKKDP7 # Qd4qOQ3dVyHAX9jLmVkB6QvAV/vTDrYTsAxaF/EaoLOy0IoKhjTvgda3XzE1MFKA # gVafLluADIfSEdqa2QR2ExL8d1SZVoiObCp5TMLRer0HIpg/vQZwjfdbo4BgQKL3 # 7Q6wBxcZUNqrFgspXjm5WFIrdk2rfS/79OmvpNM6SZaK6BnklntdJHJHtAWujGsm # EM310AUFpHMp2h6Nqnemb3qr5l4d20KSt8DhoPAUq1IE59Kb8XY= # =0iQW # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Dec 2024 20:54:00 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241220' of https://github.com/alistair23/qemu: (39 commits) target/riscv: add support for RV64 Xiangshan Nanhu CPU target/riscv: add ssstateen target/riscv/tcg: hide warn for named feats when disabling via priv_ver target/riscv: Include missing headers in 'internals.h' target/riscv: Include missing headers in 'vector_internals.h' target/riscv: Check svukte is not enabled in RV32 target/riscv: Expose svukte ISA extension target/riscv: Check memory access to meet svukte rule target/riscv: Support hstatus[HUKTE] bit when svukte extension is enabled target/riscv: Support senvcfg[UKTE] bit when svukte extension is enabled target/riscv: Add svukte extension capability variable hw/riscv: Add the checking if DTB overlaps to kernel or initrd hw/riscv: Add a new struct RISCVBootInfo hw/riscv: Support to load DTB after 3GB memory on 64-bit system. hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accesses hw/char/riscv_htif: Explicit little-endian implementation MAINTAINERS: Cover RISC-V HTIF interface tests/qtest/bios-tables-test: Update virt SPCR golden reference for RISC-V hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4 format qtest: allow SPCR acpi table changes ... Conflicts: target/riscv/cpu.c Merge conflict with DEFINE_PROP_END_OF_LIST() removal. No Property array terminator is needed anymore. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé7-10/+10
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-12-20hw/char/riscv_htif: Clarify MemoryRegionOps expect 32-bit accessesPhilippe Mathieu-Daudé1-0/+4
Looking at htif_mm_ops[] read/write handlers, we notice they expect 32-bit values to accumulate into to the 'fromhost' and 'tohost' 64-bit variables. Explicit by setting the .impl min/max fields. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241129154304.34946-4-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-20hw/char/riscv_htif: Explicit little-endian implementationPhilippe Mathieu-Daudé1-5/+6
Since our RISC-V system emulation is only built for little endian, the HTIF device aims to interface with little endian memory accesses, thus we can explicit htif_mm_ops:endianness being DEVICE_LITTLE_ENDIAN. In that case tswap64() is equivalent to le64_to_cpu(), as in "convert this 64-bit little-endian value into host cpu order". Replace to simplify. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20241129154304.34946-3-philmd@linaro.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-12-19include/hw/qdev-properties: Remove DEFINE_PROP_END_OF_LISTRichard Henderson36-38/+0
Now that all of the Property arrays are counted, we can remove the terminator object from each array. Update the assertions in device_class_set_props to match. With struct Property being 88 bytes, this was a rather large form of terminator. Saves 30k from qemu-system-aarch64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Link: https://lore.kernel.org/r/20241218134251.4724-21-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-12-15hw/char: Constify all PropertyRichard Henderson36-38/+38
Acked-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-11-07hw/char/sifive_uart: Fix broken UART on big endian hostsThomas Huth1-1/+2
Casting a "uint32_t *" to a "uint8_t *" to get to the lowest 8-bit part of the value does not work on big endian hosts. We've got to take the proper detour through an 8-bit variable. Fixes: 53c1557b23 ("hw/char: sifive_uart: Print uart characters async") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20241104163504.305955-1-thuth@redhat.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-30hw/char: sifive_uart: Print uart characters asyncAlistair Francis1-6/+91
The current approach of using qemu_chr_fe_write() and ignoring the return values results in dropped characters [1]. Let's update the SiFive UART to use a async sifive_uart_xmit() function to transmit the characters and apply back pressure to the guest with the SIFIVE_UART_TXFIFO_FULL status. This should avoid dropped characters and more realisticly model the hardware. 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910045419.1252277-3-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-30hw/char: riscv_htif: Use blocking qemu_chr_fe_write_allAlistair Francis1-2/+10
The current approach of using qemu_chr_fe_write() and ignoring the return values results in dropped characters [1]. Ideally we want to report FIFO status to the guest, but the HTIF isn't a real UART, so we don't really have a way to do that. Instead let's just use qemu_chr_fe_write_all() so at least we don't drop characters. 1: https://gitlab.com/qemu-project/qemu/-/issues/2114 Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910045419.1252277-2-alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-10-15hw/char/pl011: Use correct masks for IBRD and FBRDPeter Maydell1-2/+2
In commit b88cfee90268cad we defined masks for the IBRD and FBRD integer and fractional baud rate divider registers, to prevent the guest from writing invalid values which could cause division-by-zero. Unfortunately we got the mask values the wrong way around: the FBRD register is six bits and the IBRD register is 16 bits, not vice-versa. You would only run into this bug if you programmed the UART to a baud rate of less than 9600, because for 9600 baud and above the IBRD value will fit into 6 bits, as per the table in https://developer.arm.com/documentation/ddi0183/g/programmers-model/register-descriptions/fractional-baud-rate-register--uartfbrd The only visible effects would be that the value read back from the register by the guest would be truncated, and we would print an incorrect baud rate in the debug logs. Cc: qemu-stable@nongnu.org Fixes: b88cfee90268 ("hw/char/pl011: Avoid division-by-zero in pl011_get_baudrate()") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2610 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20241007144732.2491331-1-peter.maydell@linaro.org
2024-10-04Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingPeter Maydell7-128/+164
* pc: Add a description for the i8042 property * kvm: support for nested FRED * tests/unit: fix warning when compiling test-nested-aio-poll with LTO * kvm: refactoring of VM creation * target/i386: expose IBPB-BRTYPE and SBPB CPUID bits to the guest * hw/char: clean up serial * remove virtfs-proxy-helper * target/i386/kvm: Report which action failed in kvm_arch_put/get_registers * qom: improvements to object_resolve_path*() # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmb++MsUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroPVnwf/cdvfxvDm22tEdlh8vHlV17HtVdcC # Hw334M/3PDvbTmGzPBg26lzo4nFS6SLrZ8ETCeqvuJrtKzqVk9bI8ssZW5KA4ijM # nkxguRPHO8E6U33ZSucc+Hn56+bAx4I2X80dLKXJ87OsbMffIeJ6aHGSEI1+fKVh # pK7q53+Y3lQWuRBGhDIyKNuzqU4g+irpQwXOhux63bV3ADadmsqzExP6Gmtl8OKM # DylPu1oK7EPZumlSiJa7Gy1xBqL4Rc4wGPNYx2RVRjp+i7W2/Y1uehm3wSBw+SXC # a6b7SvLoYfWYS14/qCF4cBL3sJH/0f/4g8ZAhDDxi2i5kBr0/5oioDyE/A== # =/zo4 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 03 Oct 2024 21:04:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) qom: update object_resolve_path*() documentation qom: set *ambiguous on all paths qom: rename object_resolve_path_type() "ambiguousp" target/i386/kvm: Report which action failed in kvm_arch_put/get_registers kvm: Allow kvm_arch_get/put_registers to accept Error** accel/kvm: refactor dirty ring setup minikconf: print error entirely on stderr 9p: remove 'proxy' filesystem backend driver hw/char: Extract serial-mm hw/char/serial.h: Extract serial-isa.h hw: Remove unused inclusion of hw/char/serial.h target/i386: Expose IBPB-BRTYPE and SBPB CPUID bits to the guest kvm: refactor core virtual machine creation into its own function kvm/i386: replace identity_base variable with a constant kvm/i386: refactor kvm_arch_init and split it into smaller functions kvm: replace fprintf with error_report()/printf() in kvm_init() kvm/i386: fix return values of is_host_cpu_intel() kvm/i386: make kvm_filter_msr() and related definitions private to kvm module hw/i386/pc: Add a description for the i8042 property tests/unit: remove block layer code from test-nested-aio-poll ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/arm/Kconfig # hw/arm/pxa2xx.c
2024-10-03hw/char: Extract serial-mmBernhard Beschow5-127/+163
hw/char/serial currently contains the implementation of both TYPE_SERIAL and TYPE_SERIAL_MM. According to serial_class_init(), TYPE_SERIAL is an internal class while TYPE_SERIAL_MM is used by numerous machine types directly. Let's move the latter into its own module which makes the dependencies more obvious and the code more tidy. The includes and the dependencies have been converted mechanically except in the hw/char directories which were updated manually. The result was compile-tested. Now, only hw/char makes direct use of TYPE_SERIAL: # grep -r -e "select SERIAL" | grep -v SERIAL_ hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL hw/char/Kconfig: select SERIAL # grep -r -e "/serial\\.h" include/hw/char/serial-mm.h:#include "hw/char/serial.h" hw/char/serial-pci-multi.c:#include "hw/char/serial.h" hw/char/serial.c:#include "hw/char/serial.h" hw/char/serial-isa.c:#include "hw/char/serial.h" hw/char/serial-pci.c:#include "hw/char/serial.h" Tested-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-4-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw/char/serial.h: Extract serial-isa.hBernhard Beschow1-0/+1
The includes where updated based on compile errors. Now, the inclusion of the header roughly matches Kconfig dependencies: # grep -r -e "select SERIAL_ISA" hw/ppc/Kconfig: select SERIAL_ISA hw/isa/Kconfig: select SERIAL_ISA hw/sparc64/Kconfig: select SERIAL_ISA hw/i386/Kconfig: select SERIAL_ISA hw/i386/Kconfig: select SERIAL_ISA # for serial_hds_isa_init() Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-3-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw: Remove unused inclusion of hw/char/serial.hBernhard Beschow1-1/+0
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Link: https://lore.kernel.org/r/20240905073832.16222-2-shentey@gmail.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-10-03hw/char: Remove unused serial_set_frequencyDr. David Alan Gilbert1-7/+0
serial_set_frequnecy has been unused since it was added in 2009: 038eaf82c8 ("serial: Add interface to set reference oscillator frequency") It looks like the 'baudbase' is now a property anyway so the wrapper isn't needed. Remove it. Signed-off-by: Dr. David Alan Gilbert <dave@treblig.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-10-01hw/char: Remove omap2_uartPeter Maydell1-113/+0
Remove the OMAP2 specific code from omap_uart.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240903160751.4100218-40-peter.maydell@linaro.org
2024-09-19hw/char/stm32l4x5_usart.c: Enable USART ACK bit responseJacob Abrams1-0/+16
SW modifying USART_CR1 TE bit should cuase HW to respond by altering USART_ISR TEACK bit, and likewise for RE and REACK bit. This resolves some but not all issues necessary for the official STM USART HAL driver to function as is. Fixes: 87b77e6e01ca ("hw/char/stm32l4x5_usart: Enable serial read and write") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2540 Signed-off-by: Jacob Abrams <satur9nine@gmail.com> Message-id: 20240911043255.51966-1-satur9nine@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-09-13hw/char: replace assert(0) with g_assert_not_reached()Pierrick Bouvier1-1/+1
Use of assert(false) can trip spurious control flow warnings from some versions of GCC (i.e. using -fsanitize=thread with gcc-12): error: control reaches end of non-void function [-Werror=return-type] default: assert(0); | } | ^ Solve that by unifying the code base on g_assert_not_reached() instead. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20240910221606.1817478-5-pierrick.bouvier@linaro.org> [PMD: Add description suggested by Eric Blake] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char/escc: convert Sun mouse to use QemuInputHandlerMark Cave-Ayland1-22/+66
Update the Sun mouse implementation to use QemuInputHandler instead of the legacy qemu_add_mouse_event_handler() function. Note that this conversion adds extra sunmouse_* members to ESCCChannelState but they are not added to the migration stream (similar to the Sun keyboard members). If this were desired in future, the Sun devices should be split into separate devices and added to the migration stream there instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2518 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Carl Hauser <chauser@pullman.com> Message-ID: <20240904102301.175706-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-09-13hw/char/pl011: Rename RX FIFO methodsPhilippe Mathieu-Daudé2-8/+8
In preparation of having a TX FIFO, rename the RX FIFO methods. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240719181041.49545-12-philmd@linaro.org>
2024-09-13hw/char/pl011: Warn when using disabled transmitterPhilippe Mathieu-Daudé1-1/+10
We shouldn't transmit characters when the full UART or its transmitter is disabled. However we don't want to break the possibly incomplete "my first bare metal assembly program"s, so we choose to simply display a warning when this occurs. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240719181041.49545-9-philmd@linaro.org>
2024-09-13hw/char/pl011: Extract pl011_read_rxdata() from pl011_read()Philippe Mathieu-Daudé1-17/+24
To keep MemoryRegionOps read/write handlers with similar logic, factor pl011_read_txdata() out of pl011_read(), similar to what the previous commit did to pl011_write(). No functional change intended. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240719181041.49545-8-philmd@linaro.org>
2024-09-13hw/char/pl011: Extract pl011_write_txdata() from pl011_write()Philippe Mathieu-Daudé1-7/+15
When implementing FIFO, this code will become more complex. Start by factoring it out to a new pl011_write_txdata() function. No functional change intended. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240719181041.49545-7-philmd@linaro.org>
generated by cgit v1.1 at 2025-04-07 11:21:05 +0000