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AgeCommit message (Expand)AuthorFilesLines
2017-10-06hw/arm/xlnx-zynqmp: Mark the "xlnx, zynqmp" device with user_creatable = falseThomas Huth1-0/+2
2017-09-27migration: pre_save return intDr. David Alan Gilbert2-2/+6
2017-09-23Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell1-5/+4
2017-09-22memory: Get rid of address_space_init_shareableAlexey Kardashevskiy1-5/+4
2017-09-21msf2: Add Emcraft's Smartfusion2 SOM kitSubbaraya Sundeep2-1/+106
2017-09-21msf2: Add Smartfusion2 SoCSubbaraya Sundeep2-0/+239
2017-09-21hw/arm/omap2.c: Don't use old_mmioPeter Maydell1-12/+37
2017-09-21hw/arm/palm.c: Don't use old_mmio for static_opsPeter Maydell1-20/+10
2017-09-20Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request...Peter Maydell28-293/+113
2017-09-19numa: cpu: calculate/set default node-ids after all -numa CLI options are parsedIgor Mammedov1-8/+6
2017-09-19General warn report fixupsAlistair Francis1-1/+1
2017-09-19Convert multi-line fprintf() to warn_report()Alistair Francis1-2/+2
2017-09-19arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directlyIgor Mammedov28-260/+107
2017-09-19cpu: make cpu_generic_init() abort QEMU on errorIgor Mammedov5-25/+0
2017-09-14mps2-an511: Fix wiring of UART overflow interrupt linesPeter Maydell1-2/+2
2017-09-14hw/arm/virt: Set INTx/gsi mappingPranavkumar Sawargaonkar1-0/+1
2017-09-14xlnx-zcu102: Mark the EP108 machine as deprecatedAlistair Francis1-1/+1
2017-09-14xlnx-zcu102: Add a machine level virtualization propertyAlistair Francis2-2/+31
2017-09-14xlnx-zcu102: Add a machine level secure propertyAlistair Francis1-0/+32
2017-09-14xlnx-zcu102: Manually create the machinesAlistair Francis1-7/+67
2017-09-14xlnx-ep108: Rename to ZCU102Alistair Francis2-16/+16
2017-09-07hw/arm: Set ignore_memory_transaction_failures for most ARM boardsPeter Maydell27-0/+43
2017-09-07hw/arm/allwinner-a10: Mark the allwinner-a10 device with user_creatable = falseThomas Huth1-0/+2
2017-09-07xlnx_zynqmp: Convert to DEFINE_PROP_LINKFam Zheng1-5/+2
2017-09-07armv7m: Convert armv7m.memory to DEFINE_PROP_LINKFam Zheng1-6/+2
2017-09-07armv7m: Convert bitband.source-memory to DEFINE_PROP_LINKFam Zheng1-6/+2
2017-09-04hw/arm/digic: Mark device with user_creatable = falseThomas Huth1-0/+2
2017-09-04hw/arm/aspeed_soc: Mark devices as user_creatable = falseThomas Huth1-0/+2
2017-09-04aspeed_soc: Propagate silicon-rev to watchdogAndrew Jeffery1-0/+2
2017-09-04target/arm/kvm: pmu: improve error handlingAndrew Jones1-6/+3
2017-09-04hw/arm/virt: allow pmu instantiation with userspace irqchipAndrew Jones1-1/+2
2017-09-04target/arm/kvm: pmu: split init and set-irq stagesAndrew Jones1-2/+9
2017-09-04hw/arm/virt: add pmu interrupt stateAndrew Jones1-0/+3
2017-09-04hw/arm: use defined type name instead of hard-coded stringPhilippe Mathieu-Daudé6-18/+27
2017-09-01arm: replace cpu_arm_init() with cpu_generic_init()Igor Mammedov5-6/+6
2017-08-07hw/arm/virt: Add 2.10 machine typeEric Auger1-2/+17
2017-07-31docs: fix broken paths to docs/devel/tracing.txtPhilippe Mathieu-Daudé1-1/+1
2017-07-24integratorcp: Don't migrate flash using vmstate_register_ram_global()Peter Maydell1-2/+1
2017-07-24mps2: Correctly set parent bus for SCC devicePeter Maydell1-1/+1
2017-07-24fsl_imx*: Migrate ROM contentsPeter Maydell3-6/+6
2017-07-17hw/arm/mps2: Add ethernetPeter Maydell1-1/+9
2017-07-17hw/arm/mps2: Add SCCPeter Maydell1-1/+16
2017-07-17hw/arm/mps2: Add timersPeter Maydell1-0/+4
2017-07-17hw/arm/mps2: Add UARTsPeter Maydell1-0/+88
2017-07-17hw/arm/mps2: Implement skeleton mps2-an385 and mps2-an511 board modelsPeter Maydell2-0/+271
2017-07-14hw: Use new memory_region_init_{ram, rom, rom_device}() functionsPeter Maydell21-68/+35
2017-07-14memory: Rename memory_region_init_rom() and _rom_device() to _nomigrate()Peter Maydell4-7/+7
2017-07-14memory: Rename memory_region_init_ram() to memory_region_init_ram_nomigrate()Peter Maydell24-36/+36
2017-07-14Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2-3/+4
2017-07-14char: avoid chardevice direct accessAnton Nefedov1-1/+1
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