aboutsummaryrefslogtreecommitdiff
path: root/hw/arm/sbsa-ref.c
AgeCommit message (Expand)AuthorFilesLines
2024-05-30arm/sbsa-ref: move to Neoverse-N2 as defaultMarcin Juszkiewicz1-1/+1
2024-04-30hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM propertyPeter Maydell1-0/+1
2024-04-30hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHzPeter Maydell1-0/+15
2024-02-27hw/arm/sbsa-ref: Simplify init since PCIe is always enabledMarcin Juszkiewicz1-3/+2
2024-02-27hw/ide: Remove last two uses of ide/internal.h outside of hw/ide/BALATON Zoltan1-1/+1
2024-02-27hw/arm/sbsa-ref: Do not open-code ahci_ide_create_devs()Philippe Mathieu-Daudé1-10/+1
2024-02-15hw/ide/ahci: Move SysBus definitions to 'ahci-sysbus.h'Philippe Mathieu-Daudé1-0/+1
2024-02-02hw/arm/sbsa-ref: use pci_init_nic_devices()David Woodhouse1-3/+1
2024-01-26target/arm: Move GTimer definitions to new 'gtimer.h' headerPhilippe Mathieu-Daudé1-0/+1
2024-01-26target/arm: Move ARM_CPU_IRQ/FIQ definitions to 'cpu-qom.h' headerPhilippe Mathieu-Daudé1-0/+1
2024-01-26target/arm: Rename arm_cpu_mp_affinityRichard Henderson1-1/+1
2024-01-05hw/arm/sbsa-ref: Check CPU type in machine_run_board_init()Gavin Shan1-26/+10
2023-11-10hw/arm/sbsa-ref: Use qdev_prop_set_array()Kevin Wolf1-2/+5
2023-10-27target/arm: Implement Neoverse N2 CPU modelPeter Maydell1-0/+1
2023-10-19hw/arm/sbsa-ref: use bsa.h for PPI definitionsLeif Lindholm1-12/+9
2023-09-21sbsa-ref: add non-secure EL2 virtual timerMarcin Juszkiewicz1-0/+2
2023-07-17hw/arm/sbsa-ref: set 'slots' property of xhciYuquan Wang1-0/+1
2023-07-08hw: Simplify calls to pci_nic_init_nofail()Thomas Huth1-7/+1
2023-07-06target/arm: Define neoverse-v1Peter Maydell1-0/+1
2023-07-04hw/arm/sbsa-ref: use XHCI to replace EHCIYuquan Wang1-10/+13
2023-06-28hw/arm/sbsa-ref: Include missing 'sysemu/kvm.h' headerPhilippe Mathieu-Daudé1-0/+1
2023-06-28hw/intc/arm_gic: Un-inline GIC*/ITS class_name() helpersPhilippe Mathieu-Daudé1-0/+1
2023-06-26hw/arm: Validate cluster and NUMA node boundaryGavin Shan1-0/+2
2023-06-23hw/arm/sbsa-ref: add ITS support in SBSA GICShashi Mallela1-3/+30
2023-05-30hw/arm/sbsa-ref: add GIC node into DTMarcin Juszkiewicz1-1/+18
2023-05-26hw/arm: Use MachineClass->default_nic in the sbsa-ref machineThomas Huth1-1/+3
2023-05-18sbsa-ref: use Bochs graphics card instead of VGAMarcin Juszkiewicz1-1/+1
2023-05-18sbsa-ref: switch default cpu core to Neoverse-N1Marcin Juszkiewicz1-1/+1
2023-02-27hw/ide: Rename ide_create_drive() -> ide_bus_create_drive()Philippe Mathieu-Daudé1-1/+1
2023-02-03sbsa-ref: remove cortex-a76 from list of supported cpusMarcin Juszkiewicz1-1/+0
2023-02-03hw/arm: Use TYPE_ARM_SMMUV3Richard Henderson1-1/+2
2022-05-09hw/arm: add versioning to sbsa-ref machine DTLeif Lindholm1-0/+14
2022-05-09target/arm: Define neoverse-n1Richard Henderson1-0/+1
2022-05-09target/arm: Define cortex-a76Richard Henderson1-0/+1
2022-02-08hw/arm/boot: Drop nb_cpus field from arm_boot_infoPeter Maydell1-1/+0
2021-12-15hw/arm: Don't include qemu-common.h unnecessarilyPeter Maydell1-1/+0
2021-10-20hw/arm/sbsa-ref: Fixed cpu type error message typo.Shuuichirou Ishii1-1/+1
2021-08-25sbsa-ref: Rename SBSA_GWDT enum valueEduardo Habkost1-3/+3
2021-08-02hw/arm/boot: Report error if there is no fw_cfg device in the machinePeter Maydell1-7/+0
2021-05-02Do not include exec/address-spaces.h if it's not really necessaryThomas Huth1-1/+0
2021-03-05sbsa-ref: add 'max' to list of allowed cpusMarcin Juszkiewicz1-0/+1
2021-03-05sbsa-ref: remove cortex-a53 from list of supported cpusMarcin Juszkiewicz1-1/+0
2020-12-10vl: extract softmmu/datadir.cPaolo Bonzini1-0/+1
2020-12-10arm: remove bios_namePaolo Bonzini1-0/+2
2020-12-10sbsa-ref: allow to use Cortex-A53/57/72 cpusMarcin Juszkiewicz1-3/+20
2020-10-27hw/arm/sbsa-ref: add SBSA watchdog deviceShashi Mallela1-0/+23
2020-10-08hw/arm/sbsa-ref : allocate IRQs for SMMUv3Graeme Gregory1-0/+1
2020-10-08hw/arm/sbsa-ref : Fix SMMUv3 InitialisationGraeme Gregory1-1/+1
2020-09-30move MemMapEntryGerd Hoffmann1-5/+0
2020-09-22qom: simplify object_find_property / object_class_find_propertyDaniel P. Berrangé1-1/+1