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path: root/hw/arm/aspeed_ast10x0.c
AgeCommit message (Expand)AuthorFilesLines
2022-07-14aspeed: Refactor UART init for multi-SoC machinesPeter Delevoryas1-1/+7
2022-07-14aspeed: Create SRAM name from first CPU indexPeter Delevoryas1-1/+4
2022-06-30hw/misc/aspeed: Add PECI controllerPeter Delevoryas1-0/+13
2022-06-30aspeed: Map unimplemented devices in SoC memoryPeter Delevoryas1-6/+10
2022-06-30aspeed: Remove usage of sysbus_mmio_mapPeter Delevoryas1-12/+13
2022-06-30aspeed: Add memory property to Aspeed SoCPeter Delevoryas1-3/+2
2022-06-22aspeed: Add I2C buses to AST1030 modelTroy Lee1-0/+18
2022-05-25hw/gpio: Add ASPEED GPIO model for AST1030Jamin Lin1-0/+11
2022-05-25hw: aspeed: Introduce common UART init functionPeter Delevoryas1-5/+2
2022-05-25hw: aspeed: Ensure AST1030 respects uart-defaultPeter Delevoryas1-3/+3
2022-05-25hw: aspeed: Add uarts_num SoC attributePeter Delevoryas1-0/+1
2022-05-25hw: aspeed: Add missing UART'sPeter Delevoryas1-0/+24
2022-05-25aspeed: Introduce a get_irq AspeedSoCClass methodCédric Le Goater1-2/+3
2022-05-02aspeed/soc : Add AST1030 supportSteven Lee1-0/+299
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