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14 daysdocs: Fix Aspeed titleCédric Le Goater1-0/+1
commit ad8e0e8a0088 removed the "======" underlining the file title which broke documentation rendering. Add it back. Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc") Cc: Ed Tanous <etanous@nvidia.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Ed Tanous <etanous@nvidia.com> Message-id: 20250715061904.97540-1-clg@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-11docs/system: arm: Add max78000 board descriptionJackson Donaldson1-0/+37
This adds the target guide for the max78000FTHR Signed-off-by: Jackson Donaldson <jcksn@duck.com> Message-id: 20250711110626.624534-2-jcksn@duck.com [PMM: Moved doc to correct place in index; made underlines correct length; added missing trailing newline; added SPDX] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-08hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxlJonathan Cameron1-0/+9
Code based on i386/pc enablement. The memory layout places space for 16 host bridge register regions after the GIC_REDIST2 in the extended memmap. This is a hole in the current map so adding them here has no impact on placement of other memory regions (tested with enough CPUs for GIC_REDIST2 to be in use.) The high memory map is GiB aligned so the hole is there whatever the size of memory or device_memory below this point. The CFMWs are placed above the extended memmap. Note the existing variable highest_gpa is the highest GPA that has been allocated at a particular point in setting up the memory map. Whilst this caused some confusion in review there are existing comments explaining this so nothing is added. The cxl_devices_state.host_mr provides a small space in which to place the individual host bridge register regions for whatever host bridges are allocated via -device pxb-cxl on the command line. The existing dynamic sysbus infrastructure is not reused because pxb-cxl is a PCI device not a sysbus one but these registers are directly in the main memory map, not the PCI address space. Only create the CEDT table if cxl=on set for the machine. Default to off. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Tested-by: Itaru Kitayama <itaru.kitayama@fujitsu.com> Tested-by: Li Zhijian <lizhijian@fujitsu.com> Message-id: 20250703104110.992379-4-Jonathan.Cameron@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-07Merge tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi1-0/+6
staging target-arm queue: * Implement emulation of SME2p1 and SVE2p1 * Correctly enforce alignment checks for v8M loads and stores done via helper functions * Mark the "highbank" and the "midway" machine as deprecated # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhoABMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3n5CD/9esli7dCvutRUv0YCDR0ca # HyFgZT5Z+rnjdUgIBWk3qPIdmQ+dCvK8gci8Du8mY7WWPvJFc+x2wE9b0trxaARZ # ckjPo/dPq18FPRqppbNo5LGeBImwVqMYioJtuLIDw6vdMlm6eYvyyJWoFo6pXXPY # 3FlW0vBWZ78/KlQ8dYVK8TQryT2qswjXqvhz96/wCFQWRyWCXNosgETGQQH2z/20 # y5qAMkmI3NATaSSnkVox88RipFSnqotKSpczG5MBXs/n4hZvMHHNfrNxgZ17lygP # WI4R5j/M3cRHnglRzxVm5xzz0Vy8gWV+Zn97YMN2syJhze2nFQDcD6dWGNEYdCgT # R83/FF2yVn7v4ZompmyL97eUtfiFR/t40M+ojdhrfwADNelAU0JbeLahJuJjXfBm # ptdiTnDXYD8Ts6X+FTCafWO9ciPmPJ+SyXOcDnRpy8NpNstL6e7Um5BU8Tcw41nV # cAP5K5LooQO6yDkrVf2sjFCU9QxamPhCck+xQsT85njy3br3OA2MTGA/ZdD5noet # i2EIcdovQjMZqRv/P8c/+WzDhUw27fPbMzLOvl+nUHQM29Mx7hdTvbdvj/CiQtpV # wXprWqdG6jeAXeIkhwFs6/8Uc+7mn3guPi8RQZ5uwX5e1pYNSVOKMjGpooVekNbL # qjb+ZLPXIpkCV3N5Vbg9Uw== # =onnF # -----END PGP SIGNATURE----- # gpg: Signature made Fri 04 Jul 2025 12:23:47 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250704' of https://gitlab.com/pm215/qemu: (119 commits) linux-user/aarch64: Set hwcap bits for SME2p1/SVE2p1 target/arm: Enable FEAT_SME2p1 on -cpu max target/arm: Implement SME2 BFMOPA (non-widening) target/arm: Implement FMOPA (non-widening) for fp16 target/arm: Support FPCR.AH in SME FMOPS, BFMOPS target/arm: Rename BFMOPA to BFMOPA_w target/arm: Rename FMOPA_h to FMOPA_w_h target/arm: Implement LUTI2, LUTI4 for SME2/SME2p1 target/arm: Implement MOVAZ for SME2p1 target/arm: Implement LD1Q, ST1Q for SVE2p1 target/arm: Implement {LD, ST}[234]Q for SME2p1/SVE2p1 target/arm: Move ld1qq and st1qq primitives to sve_ldst_internal.h target/arm: Implement {LD1, ST1}{W, D} (128-bit element) for SVE2p1 target/arm: Split the ST_zpri and ST_zprr patterns target/arm: Implement SME2 counted predicate register load/store target/arm: Implement TBLQ, TBXQ for SME2p1/SVE2p1 target/arm: Implement ZIPQ, UZPQ for SME2p1/SVE2p1 target/arm: Implement PMOV for SME2p1/SVE2p1 target/arm: Implement EXTQ for SME2p1/SVE2p1 target/arm: Implement DUPQ for SME2p1/SVE2p1 ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-04target/arm: Enable FEAT_SME2p1 on -cpu maxRichard Henderson1-0/+6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250704142112.1018902-107-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-03docs: add support for gb200-bmcEd Tanous1-2/+2
This patch updates the docs for support of gb200-bmc. Signed-off-by: Ed Tanous <etanous@nvidia.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250703144249.3348879-3-etanous@nvidia.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-25docs: Remove ast2700fc from Aspeed family boardsSteven Lee1-1/+1
The ast2700fc machine is now covered in the dedicated ast2700-evb section. Listing it in the general Aspeed board family list is redundant. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250523093144.991408-7-steven_lee@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-05docs: Add support for ast2700fc machineSteven Lee1-3/+66
- Updated Aspeed family boards list to include `ast2700fc`. - Added boot instructions for the `ast2700fc` machine. - Detailed the configuration and loading of firmware for the Cortex-A35 and Cortex-M4 processors. Signed-off-by: Steven Lee <steven_lee@aspeedtech.com> Change-Id: Id41312e9c7cf79bc55c6f24a87a7ad9993dc7261 Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-10-steven_lee@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-05docs/system/arm/aspeed: Support vbootrom for AST2700Jamin Lin1-1/+28
Using the vbootrom image support and the boot ROM binary is now passed via the -bios option, using the image located in pc-bios/ast27x0_bootrom.bin. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Nabih Estefan <nabihestefan@google.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250424075135.3715128-7-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-05-05docs/system/arm/aspeed: move AST2700 content to new sectionJamin Lin1-7/+63
Moved AST2700-related content from the general Aspeed board list into a dedicated section for Aspeed 2700 family boards. Improves clarity and readability. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250424075135.3715128-6-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-04-08hw/arm/imx8mp-evk: Remove unimplemented cpu-idle-states properties from ↵Guenter Roeck1-10/+2
devicetree The cpu-idle-states property causes a hard boot hang. Rather than documenting the workaround, perform the removal from the devicetree automatically. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Bernhard Beschow <shentey@gmail.com> [Bernhard: split patch, update documentation, adapt commit message] Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-ID: <20250405214900.7114-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-04-08docs/arm: Add apple HVF host for supported guest CPU typeZhang Chen1-2/+2
In my test, latest QEMU already support Apple HVF for -cpu host and max. From guest VM lscpu: Architecture: aarch64 CPU op-mode(s): 64-bit Byte Order: Little Endian CPU(s): 11 On-line CPU(s) list: 0-10 Vendor ID: Apple Model name: - Model: 0 Thread(s) per core: 1 Core(s) per socket: 11 Socket(s): 1 Stepping: 0x0 BogoMIPS: 48.00 Flags: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm jscvt fcma lrcpc dcpop sha3 asimddp sha512 asim dfhm dit uscat ilrcpc flagm ssbs sb paca pacg dcpodp flagm2 frint Signed-off-by: Zhang Chen <zhangckid@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-ID: <20250401083102.72845-1-zhangckid@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-03-19docs/system/arm: Use "functional tests" instead of "integration tests"Thomas Huth2-6/+6
We don't use the term "integration tests" for these kind of tests anymore, it's "functional tests" nowadays. Suggested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-ID: <20250318061420.20378-1-thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-19docs/system: Use the meson binary from the pyvenvThomas Huth2-2/+2
To avoid problems with the meson installation from the host system, we should always use the meson from our venv instead. Thus use this in the documentation, too. While we're at it, also mention that it has to be run from the build folder (in the igb.rst file; the other two files were already fine). Suggested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-ID: <20250318055415.16501-1-thuth@redhat.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-12docs/system: Fix the information on how to run certain functional testsThomas Huth2-6/+5
The tests have been converted to the functional framework, so we should not talk about Avocado here anymore. Fixes: f7d6b772200 ("tests/functional: Convert BananaPi tests to the functional framework") Fixes: 380f7268b7b ("tests/functional: Convert the OrangePi tests to the functional framework") Fixes: 4c0a2df81c9 ("tests/functional: Convert some tests that download files via fetch_asset()") Message-ID: <20250311160847.388670-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2025-03-04hw/vmapple/vmapple: Add vmapple machine typeAlexander Graf1-0/+65
Apple defines a new "vmapple" machine type as part of its proprietary macOS Virtualization.Framework vmm. This machine type is similar to the virt one, but with subtle differences in base devices, a few special vmapple device additions and a vastly different boot chain. This patch reimplements this machine type in QEMU. To use it, you have to have a readily installed version of macOS for VMApple, run on macOS with -accel hvf, pass the Virtualization.Framework boot rom (AVPBooter) in via -bios, pass the aux and root volume as pflash and pass aux and root volume as virtio drives. In addition, you also need to find the machine UUID and pass that as -M vmapple,uuid= parameter: $ qemu-system-aarch64 -accel hvf -M vmapple,uuid=0x1234 -m 4G \ -bios /System/Library/Frameworks/Virtualization.framework/Versions/A/Resources/AVPBooter.vmapple2.bin -drive file=aux,if=pflash,format=raw \ -drive file=root,if=pflash,format=raw \ -drive file=aux,if=none,id=aux,format=raw \ -device vmapple-virtio-blk-pci,variant=aux,drive=aux \ -drive file=root,if=none,id=root,format=raw \ -device vmapple-virtio-blk-pci,variant=root,drive=root With all these in place, you should be able to see macOS booting successfully. Known issues: - Currently only macOS 12 guests are supported. The boot process for 13+ will need further investigation and adjustment. Signed-off-by: Alexander Graf <graf@amazon.com> Co-authored-by: Phil Dennis-Jordan <phil@philjordan.eu> Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Tested-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-ID: <20241223221645.29911-15-phil@philjordan.eu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add USB supportBernhard Beschow1-0/+1
Split the USB MMIO regions to better keep track of the implemented vs. unimplemented regions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-16-shentey@gmail.com [PMM: drop "static const" from usb_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add Ethernet controllerBernhard Beschow1-0/+1
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one and a Designware one. There is no device model for the latter, so only add the ENET one. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-15-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Implement general purpose timersBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-14-shentey@gmail.com [PMM: drop static const from gpt_attrs for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add watchdog supportBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-13-shentey@gmail.com [PMM: drop static const from wdog_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add SPI controllersBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-12-shentey@gmail.com [PMM: drop static const from spi_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add I2C controllersBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-11-shentey@gmail.com [PMM: drop static const from i2c_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add GPIO controllersBernhard Beschow1-0/+1
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-10-shentey@gmail.com [PMM: drop static const from gpio_table for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add PCIe supportBernhard Beschow1-0/+1
Linux checks for the PLLs in the PHY to be locked, so implement a model emulating that. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-9-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add USDHC storage controllersBernhard Beschow1-6/+12
The USDHC emulation allows for running real-world images such as those generated by Buildroot. Convert the board documentation accordingly instead of running a Linux kernel with ephemeral storage. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-8-shentey@gmail.com [PMM: drop 'static const' from usdhc_table[] for GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Add SNVSBernhard Beschow1-0/+1
SNVS contains an RTC which allows Linux to deal correctly with time. This is particularly useful when handling persistent storage which will be done in the next patch. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-7-shentey@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm/fsl-imx8mp: Implement clock treeBernhard Beschow1-0/+1
Fixes quite a few stack traces during the Linux boot process. Also provides the clocks for devices added later, e.g. enet1. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-6-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-25hw/arm: Add i.MX 8M Plus EVK boardBernhard Beschow1-0/+54
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller, serial. All other devices of the A53 memory map are represented as TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows for running Linux without it crashing due to invalid memory accesses. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20250223114708.1780-5-shentey@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: drop 'static const' from serial_table[] definition to avoid compile failure on GCC 7.5] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-24hw/arm/virt: Support larger highmem MMIO regionsMatthew R. Ochs1-0/+4
The MMIO region size required to support virtualized environments with large PCI BAR regions can exceed the hardcoded limit configured in QEMU. For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO (currently 512GB). Instead of updating VIRT_HIGH_PCIE_MMIO, introduce a new parameter, highmem-mmio-size, that specifies the MMIO size required to support the VM configuration. Example usage with 1TB MMIO region size: -machine virt,gic-version=3,highmem-mmio-size=1T Signed-off-by: Matthew R. Ochs <mochs@nvidia.com> Reviewed-by: Gavin Shan <gshan@redhat.com> Reviewed-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com> Message-id: 20250221145419.1281890-1-mochs@nvidia.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-20docs/system/arm: Add Description for NPCM8XX SoCHao Wu1-7/+20
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals. This document describes the NPCM8XX SoC and an evaluation board (NPCM 845 EVB). Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250219184609.1839281-18-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Enable FEAT_RPRES for -cpu maxPeter Maydell1-0/+1
Now the emulation is complete, we can enable FEAT_RPRES for the 'max' CPU type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Enable FEAT_AFP for '-cpu max'Peter Maydell1-0/+1
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we can enable FEAT_AFP for '-cpu max', and document that we support it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-01-27docs/system/arm/aspeed: Remove tacoma-bmc from the documentationThomas Huth1-2/+2
The tacoma-bmc machine has recently been removed, so let's remove it from the documentation now, too. Fixes: 2b1b66e01f ("arm: Remove tacoma-bmc machine") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250124174507.27348-1-thuth@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-01-17docs: add a glossaryPierrick Bouvier1-0/+2
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-Id: <20241209183104.365796-7-pierrick.bouvier@linaro.org> [AJB: update MAINTAINERS] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-37-alex.bennee@linaro.org>
2025-01-13docs/system/arm/virt: mention specific migration informationPierrick Bouvier1-0/+4
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241219183211.3493974-4-pierrick.bouvier@linaro.org [PMM: Removed a paragraph about using non-versioned models.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13target/arm: change default pauth algorithm to impdefPierrick Bouvier1-1/+1
Pointer authentication on aarch64 is pretty expensive (up to 50% of execution time) when running a virtual machine with tcg and -cpu max (which enables pauth=on). The advice is always: use pauth-impdef=on. Our documentation even mentions it "by default" in docs/system/introduction.rst. Thus, we change the default to use impdef by default. This does not affect kvm or hvf acceleration, since pauth algorithm used is the one from host cpu. This change is retro compatible, in terms of cli, with previous versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu max,pauth-qarma3=on is preserved. The new option introduced in previous patch and matching old default is -cpu max,pauth-qarma5=on. It is retro compatible with migration as well, by defining a backcompat property, that will use qarma5 by default for virt machine <= 9.2. Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master (10.0) for cpus neoverse-n2 and max. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-01-13target/arm: add new property to select pauth-qarma5Pierrick Bouvier1-1/+4
Before changing default pauth algorithm, we need to make sure current default one (QARMA5) can still be selected. $ qemu-system-aarch64 -cpu max,pauth-qarma5=on ... Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241219183211.3493974-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-17target/arm: Enable FEAT_XS for the max cpuManos Pitsidianakis1-0/+1
Add FEAT_XS feature report value in max cpu's ID_AA64ISAR1 sys register. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241211144440.2700268-6-peter.maydell@linaro.org [PMM: Add entry for FEAT_XS to documentation] Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-13docs/system/arm/virt: document missing propertiesPierrick Bouvier1-0/+16
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241206192254.3889131-5-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13docs/system/arm/xlnx-versal-virt: document ospi-flash propertyPierrick Bouvier1-0/+3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241206192254.3889131-4-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13docs/system/arm/fby35: document execute-in-place propertyPierrick Bouvier1-0/+5
Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241206192254.3889131-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-13docs/system/arm/orangepi: update linksPierrick Bouvier1-2/+2
www.orangepi.org does not support https, it's expected to stick to http. Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241206192254.3889131-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-12-11arm: Remove tacoma-bmc machineCédric Le Goater1-1/+0
Removal was scheduled for 10.0. Use the rainier-bmc machine or the ast2600-evb as a replacement. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20241119071352.515790-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-11-26docs/system/arm/aspeed: add missing model supermicrox11spi-bmcPierrick Bouvier1-3/+4
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Message-id: 20241122225049.1617774-13-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/fby35: update link to product pagePierrick Bouvier1-1/+1
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20241122225049.1617774-8-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/: add FEAT_DoubleLockPierrick Bouvier1-0/+1
We already implement FEAT_DoubleLock (see commit f94a6df5dd6a7) when the ID registers call for it. This feature is actually one that must *not* be implemented in v9.0, but since our documentation lists everything we can emulate, we should include FEAT_DoubleLock in the list. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Message-id: 20241122225049.1617774-7-pierrick.bouvier@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/: add FEAT_MTE_ASYNCPierrick Bouvier1-0/+1
We already implement FEAT_MTE_ASYNC; we just forgot to list it in the documentation. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241122225049.1617774-6-pierrick.bouvier@linaro.org [PMM: expand commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/emulation: add FEAT_SSBS2Pierrick Bouvier1-0/+1
We implemented this at the same times as FEAT_SSBS, but forgot to list it in the documentation. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241122225049.1617774-4-pierrick.bouvier@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: improve commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/emulation: fix typo in feature namePierrick Bouvier1-1/+1
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241122225049.1617774-3-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-11-26docs/system/arm/emulation: mention armv9Pierrick Bouvier1-3/+3
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20241122225049.1617774-2-pierrick.bouvier@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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