aboutsummaryrefslogtreecommitdiff
path: root/disas
AgeCommit message (Expand)AuthorFilesLines
2024-03-06target/riscv: honour show_opcodes when disassemblingAlex Bennée1-13/+15
2024-03-06disas/hppa: honour show_opcodesAlex Bennée1-3/+5
2024-03-06disas: introduce show_opcodesAlex Bennée1-0/+1
2024-02-11disas/hppa: Add disassembly for qemu specific instructionsHelge Deller1-0/+4
2024-01-30disas/riscv: Clean up includesPeter Maydell3-1/+2
2024-01-10disas/riscv: Add amocas.[w,d,q] instructionsRob Bradford1-0/+9
2023-11-24disas/cris: Pass buffer size to format_dec() to avoid overflow warningPhilippe Mathieu-Daudé1-10/+16
2023-11-17disas/hppa: Show hexcode of instruction along with disassemblyHelge Deller1-1/+5
2023-11-07disas/riscv: Replace TABs with spaceMax Chou1-3/+3
2023-11-07disas/riscv: Add support for vector crypto extensionsMax Chou1-0/+137
2023-11-07disas/riscv: Add rv_codec_vror_vi for vror.viMax Chou2-1/+14
2023-11-07disas/riscv: Add rv_fmt_vd_vs2_uimm formatMax Chou1-0/+1
2023-10-12disas/riscv: Fix the typo of inverted order of pmpaddr13 and pmpaddr14Alvin Chang1-2/+2
2023-09-29disas/m68k: clean up local variable shadowingLaurent Vivier1-4/+4
2023-07-19riscv/disas: Fix disas output of upper immediatesChristoph Müllner2-3/+18
2023-07-10riscv: Add support for the Zfa extensionChristoph Müllner2-0/+142
2023-07-10target/riscv: Add disas support for BF16 extensionsWeiwei Li1-0/+44
2023-07-10disas/riscv: Add support for XThead* instructionsChristoph Müllner5-0/+817
2023-07-10disas/riscv: Add support for XVentanaCondOpsChristoph Müllner4-1/+67
2023-07-10disas/riscv: Provide infrastructure for vendor extensionsChristoph Müllner1-2/+26
2023-07-10disas/riscv: Encapsulate opcode_data into decodeChristoph Müllner2-17/+25
2023-07-10disas/riscv: Make rv_op_illegal a shared enum valueChristoph Müllner2-1/+5
2023-07-10disas/riscv: Move types/constants to new header fileChristoph Müllner2-269/+283
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé1-1/+1
2023-06-13disas/riscv.c: Remove redundant parenthesesWeiwei Li1-109/+110
2023-06-13disas/riscv.c: Fix lines with over 80 charactersWeiwei Li1-61/+140
2023-06-13disas/riscv.c: Remove unused decomp_rv32/64 value for vector instructionsWeiwei Li1-370/+370
2023-06-13disas/riscv.c: Support disas for Z*inx extensionsWeiwei Li1-4/+12
2023-06-13disas/riscv.c: Support disas for Zcm* extensionsWeiwei Li1-1/+7
2023-06-13target/riscv: Pass RISCVCPUConfig as target_info to disassemble_infoWeiwei Li1-3/+7
2023-05-25disas/riscv: Decode czero.{eqz,nez}Richard Henderson1-0/+6
2023-05-11disas: Move disas.c into the target-independent source setThomas Huth2-7/+8
2023-05-11disas: Move softmmu specific code to separate fileThomas Huth4-70/+93
2023-05-11disas: Remove target-specific headersRichard Henderson1-1/+2
2023-05-11disas: Remove target_ulong from the interfaceRichard Henderson1-10/+9
2023-05-11disas: Move disas.c to disas/Richard Henderson2-1/+402
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li1-1/+227
2023-03-14Fix incorrect register name in disassembler for fmv,fabs,fneg instructionsMikhail Tyutin1-9/+10
2023-03-14disas/riscv: Fix slli_uw decodingIvan Klokov1-4/+4
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov1-1/+1
2023-02-07target/riscv: update disas.c for xnor/orn/andn and slli.uwPhilipp Tomsich1-4/+4
2023-01-13mips: Always include nanomips disassemblerPaolo Bonzini1-2/+1
2022-11-08disas/nanomips: Tidy read for 48-bit opcodesRichard Henderson1-6/+6
2022-11-08disas/nanomips: Split out read_u16Richard Henderson1-29/+19
2022-11-08disas/nanomips: Merge insn{1,2,3} into words[3]Richard Henderson1-23/+21
2022-11-08disas/nanomips: Move setjmp into nanomips_disRichard Henderson1-25/+17
2022-11-08disas/nanomips: Remove headers already included by "qemu/osdep.h"Philippe Mathieu-Daudé1-4/+0
2022-11-08disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formatsPhilippe Mathieu-Daudé1-1/+1
2022-11-08disas/nanomips: Fix invalid PRIx64 format calling img_format()Philippe Mathieu-Daudé1-1/+2
2022-11-08disas/nanomips: Fix invalid PRId64 format calling img_format()Philippe Mathieu-Daudé1-15/+20
generated by cgit v1.1 at 2024-11-02 21:20:07 +0000