riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-02-07	target/riscv: update disas.c for xnor/orn/andn and slli.uw	Philipp Tomsich	1	-4/+4
2022-10-14	disas/riscv.c: rvv: Add disas support for vector instructions	Yang Liu	1	-2/+1430
2022-09-27	target/riscv: Remove sideleg and sedeleg	Rahul Pathak	1	-2/+0
2022-09-07	target/riscv: fix shifts shamt value for rv128c	Frédéric Pétrot	1	-6/+21
2022-04-29	disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions	Weiwei Li	1	-1/+172
2022-01-08	target/riscv: setup everything for rv64 to support rv128 execution	Frédéric Pétrot	1	-0/+5
2021-10-07	disas/riscv: Add Zb[abcs] instructions	Philipp Tomsich	1	-3/+154
2019-06-27	disas/riscv: Fix `rdinstreth` constraint	Wladimir J. van der Laan	1	-2/+3
2019-06-27	disas/riscv: Disassemble reserved compressed encodings as illegal	Michael Clark	1	-17/+45
2019-04-18	disas: Rename include/disas/bfd.h back to include/disas/dis-asm.h	Markus Armbruster	1	-1/+1
2019-03-19	RISC-V: Remove unnecessary disassembler constraints	Michael Clark	1	-138/+0
2018-05-06	RISC-V: Fix missing break statement in disassembler	Michael Clark	1	-1/+2
2018-05-06	RISC-V: Include instruction hex in disassembly	Michael Clark	1	-19/+20
2018-03-28	RISC-V: Fix incorrect disassembly for addiw	Michael Clark	1	-1/+1
2018-03-07	RISC-V Disassembler	Michael Clark	1	-0/+3048