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6 daystarget/riscv: Enable RV32 CPU support in RV64 QEMUTANG Tiancheng1-1/+1
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs in RV64 QEMU. Signed-off-by: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com> Reviewed-by: Liu Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240919055048.562-7-zhiwei_liu@linux.alibaba.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
11 daysconfig/targets: update aarch64_be-linux-user gdb XML listAlex Bennée1-1/+1
Attempting to run the binary asserts when it can't find the XML entry. We can fix it so we don't although I suspect other stuff is broken. Fixes: https://gitlab.com/qemu-project/qemu/-/issues/2580 Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20241023113406.1284676-13-alex.bennee@linaro.org>
2024-10-13target/i386/gdbstub: Expose orig_axIlya Leoshkevich2-2/+2
Copy XML files describing orig_ax from GDB and glue them with CPUX86State.orig_ax. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-ID: <20240912093012.402366-5-iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-10-02Merge tag 'pull-riscv-to-apply-20241002' of ↵Peter Maydell1-0/+4
https://github.com/alistair23/qemu into staging RISC-V PR for 9.2 * Add a property to set vl to ceil(AVL/2) * Enable numamem testing for RISC-V * Consider MISA bit choice in implied rule * Fix the za64rs priv spec requirements * Enable Bit Manip for OpenTitan Ibex CPU * Fix the group bit setting of AIA with KVM * Stop timer with infinite timecmp * Add 'fcsr' register to QEMU log as a part of F extension * Fix riscv64 build on musl libc * Add preliminary textra trigger CSR functions * RISC-V bsd-user support * Respect firmware ELF entry point * Add Svvptc extension support * Fix masking of rv32 physical address * Fix linking problem with semihosting disabled * Fix IMSIC interrupt state updates # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmb83lYACgkQr3yVEwxT # gBNndBAAmh66yWt9TeTHlQ/rgBhx2nUMBbfICBWQyNGvPlslffwrNoLkh8jpkuiP # PD0RQArAAGeM09cgCZCu14JzIBmmNiGgUxsUnqOZvUw18uIlLFlpt/tiT7iGw/Xb # pfI7waF66/FPXBErY2yiw9/RGQLlkiGNBC9FNYrD/kCahf9MSIobv85tOgSQ2qjH # nOJ+UBN0TQ1x0Z5lJMj9Pzl1WDvelRnCkYI5nXg1heKG73Hm7GmHt99QpTV2Okqn # T3jFzEfMTQeHO4nC/X2pbaesE62K+mTg/FZpId2iV8lMCSm1zKof+xJ4boKM9RB2 # 0HjXAT+MveLuLUNtgfbV9C+VgU25M+wnfy5tH0l801Y/Gez8Q1fbK2uykuiyiUSy # MNNk/KzmOYuffwItuyeL3mmWHXsN+izUIeMmMxfL9X9nssZXRsrDXc+MByS7w0fk # QOeZmXHTxXwxFymr0t0DLK2eKEG6cqQty1KWp6iLx3uwnMTGo+576P41Q+boj64s # VllWzmuR0Ta0xuSR4sDvEFCO7OCFEgVdn1j0FvhRFskPEDrbQgXRLq8i3awtU6z1 # NIh+A30XeK+EZLv0sEje6gav5lZHWMfAeCOKJstVzOl8+NQibuKTUrsqLgTrBK6K # plw8qwvZYjSnYErzHfywlq9ArufIvOHYcx9Nb76tLNy9E+y01yo= # =15Hm # -----END PGP SIGNATURE----- # gpg: Signature made Wed 02 Oct 2024 06:47:02 BST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20241002' of https://github.com/alistair23/qemu: (35 commits) bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV bsd-user: Implement 'get_mcontext' for RISC-V bsd-user: Implement RISC-V signal trampoline setup functions bsd-user: Define RISC-V signal handling structures and constants bsd-user: Add generic RISC-V64 target definitions bsd-user: Define RISC-V system call structures and constants bsd-user: Define RISC-V VM parameters and helper functions bsd-user: Add RISC-V thread setup and initialization support bsd-user: Implement RISC-V sysarch system call emulation bsd-user: Add RISC-V signal trampoline setup function bsd-user: Define RISC-V register structures and register copying bsd-user: Add RISC-V ELF definitions and hardware capability detection bsd-user: Implement RISC-V TLS register setup bsd-user: Implement RISC-V CPU register cloning and reset functions bsd-user: Add RISC-V CPU execution loop and syscall handling bsd-user: Implement RISC-V CPU initialization and main loop hw/intc: riscv-imsic: Fix interrupt state updates. target/riscv/cpu_helper: Fix linking problem with semihosting disabled target/riscv32: Fix masking of physical address ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-10-02Remove the unused sh4eb targetThomas Huth1-2/+0
Since the "shix" machine has been removed, the "r2d" machine is the only machine that is still available for the sh4 and sh4eb targets. However, the "r2d" machine apparently does not work in big endian mode, see here: https://lore.kernel.org/qemu-devel/87a5fwjjew.wl-ysato@users.sourceforge.jp/ So there is no working machine left in the sh4eb-softmmu target, i.e. it is currently completely useless. Thus remove it from the configuration now. (Note: The linux-user binary is not removed since it might still be used to run sh4 binaries in big endian mode). Message-ID: <20240926105843.81385-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-10-02bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML FilesWarner Losh1-0/+4
Added configuration for RISC-V 64-bit target to the build system. Signed-off-by: Warner Losh <imp@bsdimp.com> Signed-off-by: Ajeet Singh <itachis@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240916155119.14610-18-itachis@FreeBSD.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-09-22linux-user,loongarch: move to syscalltbl fileLaurent Vivier1-0/+2
Since kernel v6.11 loongarch has moved from syscall_nr.h file to syscall.tbl (26a3b85bac08 ("loongarch: convert to generic syscall table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Remove scripts/gensyscalls.sh that is now useless. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-6-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user,hexagon: move to syscalltbl fileLaurent Vivier1-0/+2
Since kernel v6.11 hexagon has moved from syscall_nr.h file to syscall.tbl (36d69c29759e ("hexagon: use new system call table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-5-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user,riscv: move to syscalltbl fileLaurent Vivier2-0/+6
Since kernel v6.11 riscv has moved from syscall_nr.h file to syscall.tbl (3db80c999deb ("riscv: convert to generic syscall table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-4-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user,openrisc: move to syscalltbl fileLaurent Vivier1-0/+2
Since kernel v6.11 openrisc has moved from syscall_nr.h file to syscall.tbl (See 77122bf9e3df ("openrisc: convert to generic syscall table")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall.tbl instead of syscall_nr.h. New syscall.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-3-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-22linux-user,aarch64: move to syscalltbl fileLaurent Vivier2-0/+4
Since kernel v6.11 aarch64 has moved from syscall_nr.h file to syscall_64.tbl (See e632bca07c8e ("arm64: generate 64-bit syscall.tbl")) Update linux-user scripts to be able to retrieve syscall numbers from linux syscall_64.tbl instead of syscall_nr.h. New syscall_64.tbl is imported from linux v6.11 using updated scripts/update-syscalltbl.sh Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-ID: <20240920151034.859533-2-laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-09-13system: Remove support for CRIS targetPhilippe Mathieu-Daudé1-1/+0
We are about to remove the CRIS target, so remove the sysemu part. This remove the CRIS 'none' machine. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-13-philmd@linaro.org>
2024-09-13linux-user: Remove support for CRIS targetPhilippe Mathieu-Daudé1-1/+0
As per the deprecation notice in commit c7bbef4023: The CRIS architecture was pulled from Linux in 4.17 and the compiler is no longer packaged in any distro making it harder to run the `check-tcg` tests. Unless we can improve the testing situation there is a chance the code will bitrot without anyone noticing. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Message-ID: <20240904143603.52934-5-philmd@linaro.org>
2024-07-23bsd-user: Add aarch64 build to treeWarner Losh1-0/+3
Add the aarch64 bsd-user fragments needed to build the new aarch64 code. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-07-19target/loongarch/gdbstub: Add vector registers supportSong Gao2-2/+2
GDB already support LoongArch vector extension[1], QEMU gdb adds LoongArch vector registers support, so that users can use 'info all-registers' to get all vector registers values. [1]: https://sourceware.org/git/?p=binutils-gdb.git;a=commitdiff;h=1e9569f383a3d5a88ee07d0c2401bd95613c222e Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewd-by: Bibo Mao <maobibo@loongson.cn> Message-Id: <20240711024454.3075183-1-gaosong@loongson.cn>
2024-07-12target/loongarch/kvm: Add software breakpoint supportBibo Mao1-0/+1
With KVM virtualization, debug exception is injected to guest kernel rather than host for normal break intruction. Here hypercall instruction with special code is used for sw breakpoint usage, and detailed instruction comes from kvm kernel with user API KVM_REG_LOONGARCH_DEBUG_INST. Now only software breakpoint is supported, and it is allowed to insert/remove software breakpoint. We can debug guest kernel with gdb method after kernel is loaded, hardware breakpoint will be added in later. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Tested-by: Song Gao <gaosong@loongson.cn> Message-Id: <20240607035016.2975799-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2024-07-05gdbstub: Add support for MTE in user modeGustavo Romero1-1/+1
This commit implements the stubs to handle the qIsAddressTagged, qMemTag, and QMemTag GDB packets, allowing all GDB 'memory-tag' subcommands to work with QEMU gdbstub on aarch64 user mode. It also implements the get/set functions for the special GDB MTE register 'tag_ctl', used to control the MTE fault type at runtime. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20240628050850.536447-11-gustavo.romero@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-40-alex.bennee@linaro.org>
2024-06-26target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUGChao Du1-0/+1
To enable the KVM GUEST DEBUG for RISC-V at QEMU side. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-4-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-05-10configs: disable emulators that require it if libfdt is not foundPaolo Bonzini14-4/+10
Since boards can express their dependency on libfdt and system/device_tree.c, only leave TARGET_NEED_FDT if the target has a hard dependency. Those emulators will be skipped if libfdt is disabled, or if it is "auto" and not found and --disable-download is passed; unless the target is mentioned explicitly in --target-list, in which case the build will fail. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2024-04-24Merge tag 'housekeeping-20240424' of https://github.com/philmd/qemu into stagingRichard Henderson2-3/+0
Removal of deprecated code - Remove the Nios II target and hardware - Remove pvrdma device and rdmacm-mux helper - Remove GlusterFS RDMA protocol handling - Update Sriram Yagnaraman mail address # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmYpE0YACgkQ4+MsLN6t # wN5PIA//egomANjRHAUAf9tdjljgT/JR49ejM7iInyxspR/xaiq0TlP2kP6aDNps # y1HAWBwfj5lGxeMgQ1mSKJGka3v2AIPWb7RbNT+9AaiWHv+sx5OrEytozUsFHLo8 # gSgRQocq0NY2a9dPbtkDqfbmq/rkCC7wgZzwroHsyOdiqYsWDKPJFleBDMjGmEaf # colhiDmhUPgvE3NNpwfEVNh/2SzxUxY8k5FHal6qij5z56ZqBglgnziDZEvGVCZ1 # uF4Hca/kh7TV2MVsdStPbGWZYDhJ/Np/2FnRoThD1Hc4qq8d/SH997m2F94tSOud # YeH54Vp5lmCeYgba5y8VP0ZPx/b9XnTtLvKggNdoqB+T2LBWPRt8kehqoaxvammF # ALzbY/t2vUxL6nIVbosOaTyqVOXvynk3/Js5S0jbnlu+vP2WvvFEzfYKIs2DIA8w # z56o/rG4KfyxF0aDB+CvLNwtJS8THqeivPqmYoKTdN9FPpN2RyBNLITrKo389ygF # 3oWy3+xsKGIPdNFY0a4l25xntqWNhND89ejzyL9M6G1cQ9RdEmTIUGTrinPQQmfP # oHIJMBeTdj7EqPL4LB3BR/htw9U5PobeMNYKFsRkS39PjGDqba5wbIdk3w5/Rcxa # s/PKdspDKWPwZ5jhcLD0qxAGJFnqM2UFjPo+U8qyI3RXKXFAn0E= # =c8Aj # -----END PGP SIGNATURE----- # gpg: Signature made Wed 24 Apr 2024 07:12:22 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'housekeeping-20240424' of https://github.com/philmd/qemu: block/gluster: Remove deprecated RDMA protocol handling hw/rdma: Remove deprecated pvrdma device and rdmacm-mux helper hw/timer: Remove the ALTERA_TIMER model target/nios2: Remove the deprecated Nios II target MAINTAINERS: Update Sriram Yagnaraman mail address Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-24target/nios2: Remove the deprecated Nios II targetPhilippe Mathieu-Daudé2-3/+0
The Nios II target is deprecated since v8.2 in commit 9997771bc1 ("target/nios2: Deprecate the Nios II architecture"). Remove: - Buildsys / CI infra - User emulation - System emulation (10m50-ghrd & nios2-generic-nommu machines) - Tests Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Marek Vasut <marex@denx.de> Message-Id: <20240327144806.11319-3-philmd@linaro.org>
2024-04-18kvm: use configs/ definition to conditionalize debug supportPaolo Bonzini6-0/+6
If an architecture adds support for KVM_CAP_SET_GUEST_DEBUG but QEMU does not have the necessary code, QEMU will fail to build after updating kernel headers. Avoid this by using a #define in config-target.h instead of KVM_CAP_SET_GUEST_DEBUG. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-11-08default-configs: Add TARGET_XML_FILES definitionAkihiko Odaki1-0/+1
loongarch64-linux-user has references to XML files so include them. Fixes: d32688ecdb ("default-configs: Add loongarch linux-user support") Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20231030054834.39145-6-akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [AJB: remove base32 from list] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231106185112.2755262-2-alex.bennee@linaro.org>
2023-11-06target/hppa: Remove TARGET_HPPA64Richard Henderson1-0/+1
Allow both user-only and system mode to run pa2.0 cpus. Avoid creating a separate qemu-system-hppa64 binary; force the qemu-hppa binary to use TARGET_ABI32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-25configs: Enable MTTCG for sparc, sparc64Richard Henderson2-0/+2
This will be of small comfort to sparc64, because both sun4u and sun4v board models force max_cpus = 1. But it does enable actual smp for sparc32 sun4m. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-08-24target/loongarch: Add GDB support for loongarch32 modeJiajie Chen1-1/+1
GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn> [PMD: Rebased, set gdb_num_core_regs] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-9-philmd@linaro.org>
2023-05-18Hexagon (gdbstub): add HVX supportTaylor Simpson1-1/+1
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Co-authored-by: Brian Cain <bcain@quicinc.com> Signed-off-by: Brian Cain <bcain@quicinc.com> Co-authored-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Brian Cain <bcain@quicinc.com> Message-Id: <17cb32f34d469f705c3cc066a3583935352ee048.1683214375.git.quic_mathbern@quicinc.com>
2023-05-18Hexagon: add core gdbstub xml data for LLDBMatheus Tavares Bernardino1-0/+1
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <d25a3a79334d81f0e1ecfb438b6ee82585d02dc4.1683214375.git.quic_mathbern@quicinc.com>
2023-05-11target/sh4: Remove TARGET_ALIGNED_ONLYRichard Henderson4-4/+0
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/nios2: Remove TARGET_ALIGNED_ONLYRichard Henderson1-1/+0
In gen_ldx/gen_stx, the only two locations for memory operations, mark the operation as either aligned (softmmu) or unaligned (user-only, as if emulated by the kernel). Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-11target/mips: Remove TARGET_ALIGNED_ONLYRichard Henderson10-10/+0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/sparc: Remove TARGET_ALIGNED_ONLYRichard Henderson5-5/+0
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/hppa: Remove TARGET_ALIGNED_ONLYRichard Henderson2-2/+0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-05target/alpha: Remove TARGET_ALIGNED_ONLYRichard Henderson2-2/+0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-04-28s390x/gdb: Split s390-virt.xmlIlya Leoshkevich2-2/+2
Both TCG and KVM emulate ckc, cputm, last_break and prefix, and it's quite useful to have them during debugging. Right now they are grouped together with KVM-only pp, pfault_token, pfault_select and pfault_compare in s390-virt.xml, and are not available when debugging TCG-emulated code. Move KVM-only registers into the new s390-virt-kvm.xml file. Advertise s390-virt.xml always, and the new s390-virt-kvm.xml only for KVM. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Message-Id: <20230314101813.174874-1-iii@linux.ibm.com> Acked-by: David Hildenbrand <david@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2023-03-06target/arm: Implement gdbstub pauth extensionRichard Henderson3-3/+3
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK ptrace register set. The original gdb feature consists of two masks, data and code, which are used to mask out the authentication code within a pointer. Following discussion with Luis Machado, add two more masks in order to support pointers within the high half of the address space (i.e. TTBR1 vs TTBR0). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1105 Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230227213329.793795-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-02-21target/microblaze: Add gdbstub xmlRichard Henderson4-0/+4
Mirroring the upstream gdb xml files, the two stack boundary registers are separated out. Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-26configs/targets/nios2-softmmu: Add TARGET_NEED_FDT=y to the nios2 configThomas Huth1-0/+1
qemu-system-nios2 uses the functions from libfdt in hw/nios2/boot.c, so this target has to be marked with TARGET_NEED_FDT=y in its config file. Message-Id: <20230119125745.2028814-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-09-04target/openrisc: Enable MTTCGStafford Horne1-0/+1
This patch enables multithread TCG for OpenRISC. Since the or1k shared syncrhonized timer can be updated from each vCPU via helpers we use a mutex to synchronize updates. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Stafford Horne <shorne@gmail.com>
2022-08-05target/loongarch: Update loongarch-fpu.xmlSong Gao1-1/+1
Rename loongarch-fpu64.xml to loongarch-fpu.xml and update loongarch-fpu.xml to match upstream GDB [1] [1]:https://github.com/bminor/binutils-gdb/blob/master/gdb/features/loongarch/fpu.xml Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220805033523.1416837-5-gaosong@loongson.cn>
2022-07-19hw/loongarch: Add fdt supportXiaojuan Yang1-0/+1
Add LoongArch flatted device tree, adding cpu device node, firmware cfg node, pcie node into it, and create fdt rom memory region. Now fdt info is not full since only uefi bios uses fdt, linux kernel does not use fdt. Loongarch Linux kernel uses acpi table which is full in qemu virt machine. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220712083206.4187715-7-yangxiaojuan@loongson.cn> [rth: Set TARGET_NEED_FDT, add fdt to meson.build] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-04default-configs: Add loongarch linux-user supportSong Gao1-0/+3
This patch adds loongarch64 linux-user default configs file. Signed-off-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: WANG Xuerui <git@xen0n.name> Message-Id: <20220624031049.1716097-13-gaosong@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-28semihosting: Split out guestfd.cRichard Henderson6-0/+6
In arm-compat-semi.c, we have more advanced treatment of guest file descriptors than we do in other implementations. Split out GuestFD and related functions to a new file so that they can be shared. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06target/loongarch: Add gdb support.Xiaojuan Yang1-0/+1
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-42-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-06-06hw/loongarch: Add support loongson3 virt machine type.Xiaojuan Yang1-0/+3
Emulate a 3A5000 board use the new loongarch instruction. 3A5000 belongs to the Loongson3 series processors. The board consists of a 3A5000 cpu model and the virt bridge. The host 3A5000 board is really complicated and contains many functions.Now for the tcg softmmu mode only part functions are emulated. More detailed info you can see https://github.com/loongson/LoongArch-Documentation Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220606124333.2060567-31-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-04-26target/nios2: Enable unaligned traps for system modeRichard Henderson1-0/+1
Unaligned traps are optional, but required with an mmu. Turn them on always, because the fallback behaviour undefined. Enable alignment checks in the config file. Unwind the guest pc properly from do_unaligned_access. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220421151735.31996-48-richard.henderson@linaro.org>
2022-04-06Replace TARGET_WORDS_BIGENDIANMarc-André Lureau30-30/+30
Convert the TARGET_WORDS_BIGENDIAN macro, similarly to what was done with HOST_BIG_ENDIAN. The new TARGET_BIG_ENDIAN macro is either 0 or 1, and thus should always be defined to prevent misuse. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Suggested-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-8-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-02-26hw/openrisc/openrisc_sim: Add automatic device tree generationStafford Horne1-0/+1
Using the device tree means that qemu can now directly tell the kernel what hardware is configured rather than use having to maintain and update a separate device tree file. This patch adds automatic device tree generation support for the OpenRISC simulator. A device tree is built up based on the state of the configure openrisc simulator. This is then dumped to memory and the load address is passed to the kernel in register r3. Signed-off-by: Stafford Horne <shorne@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-09linux-user: Remove the deprecated ppc64abi32 targetThomas Huth1-8/+0
It's likely broken, and nobody cared for picking it up again during the deprecation phase, so let's remove this now. Since this is the last entry in deprecated_targets_list, remove the related code in the configure script, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Cédric Le Goater <clg@kaod.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20211215084958.185214-1-thuth@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220112112722.3641051-32-alex.bennee@linaro.org>
2022-01-07bsd-user: add arm target buildWarner Losh1-0/+2
CC: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-11-04 18:42:21 +0000