aboutsummaryrefslogtreecommitdiff
path: root/bsd-user/arm
AgeCommit message (Expand)AuthorFilesLines
2022-02-26bsd-user: introduce target.hWarner Losh1-0/+21
2022-02-26bsd-user/arm/target_arch_thread.h: Assume a FreeBSD targetWarner Losh1-3/+1
2022-02-26bsd-user/arm/target_arch_cpu.h: Only support FreeBSD sys callsWarner Losh1-73/+66
2022-01-30bsd-user: Rename arg name for target_cpu_reset to envWarner Losh1-1/+1
2022-01-28bsd-user/arm/target_arch_cpu.h: Implement data faultsWarner Losh1-10/+35
2022-01-28bsd-user/arm/target_arch_cpu.h: Use force_sig_fault for EXCP_UDEFWarner Losh1-12/+13
2022-01-28bsd-user/arm/target_arch_cpu.h: Correct code pointerWarner Losh1-1/+1
2022-01-28bsd-user/arm/arget_arch_cpu.h: Move EXCP_DEBUG and EXCP_BKPT togetherWarner Losh1-20/+2
2022-01-28bsd-user/signal-common.h: Move signal functions prototypes to hereWarner Losh1-0/+1
2022-01-28bsd-user/arm/target_arch_cpu.h: Move EXCP_ATOMIC to match linux-userWarner Losh1-3/+3
2022-01-28bsd-user/arm/signal.c: get_mcontext should zero vfp dataWarner Losh1-0/+9
2022-01-28bsd-user/arm/signal.c: Implement setup_sigframe_arch for armWarner Losh1-17/+33
2022-01-07bsd-user/arm/signal.c: arm get_ucontext_sigreturnWarner Losh1-0/+9
2022-01-07bsd-user/arm/signal.c: arm set_mcontextWarner Losh1-0/+76
2022-01-07bsd-user/arm/signal.c: arm get_mcontextWarner Losh1-0/+51
2022-01-07bsd-user/arm/signal.c: arm set_sigtramp_argsWarner Losh1-0/+60
2022-01-07bsd-user/arm/target_arch_signal.h: Define size of *context_tWarner Losh1-0/+3
2022-01-07bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signalsWarner Losh1-0/+28
2022-01-07bsd-user/arm/target_arch_signal.h: arm specific signal registers and stackWarner Losh1-0/+57
2022-01-07bsd-user/arm/target_arch_elf.h: arm get_hwcap2 implWarner Losh1-0/+22
2022-01-07bsd-user/arm/target_arch_elf.h: arm get hwcapWarner Losh1-1/+71
2022-01-07bsd-user/arm/target_arch_elf.h: arm defines for ELFWarner Losh1-0/+36
2022-01-07bsd-user/arm/target_arch_thread.h: Routines to create and switch to a threadWarner Losh1-0/+82
2022-01-07bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for armWarner Losh1-0/+49
2022-01-07bsd-user/arm/target_arch_vmparam.h: Parameters for arm address spaceWarner Losh1-0/+48
2022-01-07bsd-user/arm/target_arch_reg.h: Implement core dump register copyingWarner Losh1-0/+60
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement system call dispatchWarner Losh1-0/+94
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement data abort exceptionsWarner Losh1-0/+11
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptionsWarner Losh1-0/+33
2022-01-07bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementationWarner Losh1-0/+22
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regsWarner Losh1-0/+8
2022-01-07bsd-user/arm/target_arch_cpu.h: CPU Loop definitionsWarner Losh1-0/+43
2022-01-07bsd-user/arm/target_arch_cpu.c: Target specific TLS routinesWarner Losh2-0/+67
2022-01-07bsd-user/arm/target_syscall.h: Add copyright and update nameWarner Losh1-4/+23
2022-01-07bsd-user/arm/target_arch_sysarch.h: Use consistent include guardsWarner Losh1-3/+3
2021-01-11bsd-user: move strace OS/arch dependent code to host/arch dirsStacey Son2-0/+114
generated by cgit v1.1 at 2024-11-17 02:54:21 +0000