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AgeCommit message (Expand)AuthorFilesLines
2021-06-19accel/tcg: Probe the proper permissions for atomic opsRichard Henderson3-44/+83
2021-06-19accel/tcg: Add tcg call flags to plugins helpersRichard Henderson1-2/+2
2021-06-19plugins: Drop tcg_flags from struct qemu_plugin_dyn_cbRichard Henderson2-5/+4
2021-06-19accel/tcg/plugin-gen: Drop inline markersRichard Henderson1-7/+5
2021-06-13tcg: Move tcg_init_ctx and tcg_ctx from accel/tcg/Richard Henderson1-3/+0
2021-06-11accel/tcg: Pass down max_cpus to tcg_initRichard Henderson1-1/+9
2021-06-11accel/tcg: Use MiB in tcg_init_machineRichard Henderson1-1/+2
2021-06-11accel/tcg: Merge tcg_exec_init into tcg_init_machineRichard Henderson3-20/+19
2021-06-11tcg: Create tcg_initRichard Henderson1-2/+1
2021-06-11accel/tcg: Rename tcg_init to tcg_init_machineRichard Henderson1-2/+2
2021-06-11accel/tcg: Move alloc_code_gen_buffer to tcg/region.cRichard Henderson1-413/+1
2021-06-11accel/tcg: Inline cpu_gen_initRichard Henderson1-6/+1
2021-06-11tcg: Re-order tcg_region_init vs tcg_prologue_initRichard Henderson2-11/+3
2021-06-03hvf: Simplify post reset/init/loadvm hooksAlexander Graf1-20/+7
2021-06-03hvf: Introduce hvf vcpu structAlexander Graf1-2/+6
2021-06-03hvf: Remove hvf-accel-ops.hAlexander Graf2-19/+0
2021-06-03hvf: Make synchronize functions staticAlexander Graf2-6/+3
2021-06-03hvf: Use cpu_synchronize_state()Alexander Graf2-2/+1
2021-06-03hvf: Split out common code on vcpu init and destroyAlexander Graf2-2/+30
2021-06-03hvf: Remove use of hv_uvaddr_t and hv_gpaddr_tAlexander Graf1-3/+3
2021-06-03hvf: Make hvf_set_phys_mem() staticAlexander Graf1-1/+1
2021-06-03hvf: Move cpu functions into common directoryAlexander Graf1-1/+307
2021-06-03hvf: Move vcpu thread functions into common directoryAlexander Graf3-0/+170
2021-06-03hvf: Move assert_hvf_ok() into common directoryAlexander Graf3-0/+54
2021-06-02docs: fix references to docs/devel/tracing.rstStefano Garzarella2-2/+2
2021-05-28Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210526' into...Peter Maydell7-5/+166
2021-05-26accel/tcg: Keep TranslationBlock headers local to TCGPhilippe Mathieu-Daudé7-7/+166
2021-05-26accel/tcg: Reduce 'exec/tb-context.h' inclusionPhilippe Mathieu-Daudé2-0/+2
2021-05-26KVM: Dirty ring supportPeter Xu2-3/+378
2021-05-26KVM: Disable manual dirty log when dirty ring enabledPeter Xu1-14/+23
2021-05-26KVM: Add dirty-ring-size propertyPeter Xu1-0/+46
2021-05-26KVM: Cache kvm slot dirty bitmap sizePeter Xu1-0/+1
2021-05-26KVM: Simplify dirty log sync in kvm_set_phys_memPeter Xu1-1/+2
2021-05-26KVM: Provide helper to sync dirty bitmap from slot to ramblockPeter Xu1-20/+17
2021-05-26KVM: Provide helper to get kvm dirty logPeter Xu1-22/+30
2021-05-26KVM: Create the KVMSlot dirty bitmap on flag changesPeter Xu1-14/+9
2021-05-26KVM: Use a big lock to replace per-kml slots_lockPeter Xu1-15/+18
2021-05-26KVM: do not allow setting properties at runtimePaolo Bonzini1-1/+12
2021-05-25accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1]Richard Henderson1-6/+6
2021-05-25accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0Richard Henderson1-6/+5
2021-05-25accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()Richard Henderson1-7/+20
2021-05-25accel/tcg: Add tlb_flush_range_by_mmuidx_all_cpus()Richard Henderson1-7/+17
2021-05-25accel/tcg: Add tlb_flush_range_by_mmuidx()Richard Henderson1-5/+15
2021-05-25accel/tcg: Remove {encode,decode}_pbm_to_runonRichard Henderson1-66/+20
2021-05-25accel/tlb: Rename TLBFlushPageBitsByMMUIdxData -> TLBFlushRangeDataRichard Henderson1-12/+12
2021-05-25accel/tcg: Pass length argument to tlb_flush_range_locked()Richard Henderson1-15/+33
2021-05-25accel/tcg: Replace g_new() + memcpy() by g_memdup()Richard Henderson1-11/+4
2021-05-20accel/tcg: Assert that tb->size != 0 after translationIlya Leoshkevich1-0/+1
2021-05-18Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210516' into...Peter Maydell1-2/+9
2021-05-16accel/tcg: Align data dumped at end of TBPhilippe Mathieu-Daudé1-2/+9
generated by cgit v1.1 at 2024-07-19 08:15:35 +0000