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2023-09-07Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingStefan Hajnoczi1-1/+3
2023-09-07configure, meson: move --enable-plugins to mesonPaolo Bonzini1-1/+3
2023-08-31accel/tcg: spelling fixesMichael Tokarev1-1/+1
2023-08-29softmmu: Use async_run_on_cpu in tcg_commitRichard Henderson1-30/+0
2023-08-24accel/tcg: Update run_on_cpu_data static assertAnton Johansson1-2/+3
2023-08-24accel/tcg: Widen address arg in tlb_compare_set()Anton Johansson1-1/+1
2023-08-24include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*()Anton Johansson2-13/+13
2023-08-10accel/tcg: Avoid reading too much in load_atom_{2,4}Richard Henderson1-2/+8
2023-08-06accel/tcg: Call save_iotlb_data from io_readx as wellMikhail Tyutin1-15/+21
2023-08-05accel/tcg: Do not issue misaligned i/oRichard Henderson1-46/+72
2023-08-05accel/tcg: Issue wider aligned i/o in do_{ld,st}_mmio_*Richard Henderson1-7/+69
2023-08-05accel/tcg: Adjust parameters and locking with do_{ld,st}_mmio_*Richard Henderson1-33/+34
2023-07-31accel/tcg: Clear tcg_ctx->gen_tb on buffer overflowRichard Henderson1-0/+1
2023-07-24accel/tcg: Fix type of 'last' for pageflags_{find,next}Luca Bonissi1-2/+2
2023-07-24accel/tcg: Zero-pad vaddr in tlb_debug outputAnton Johansson1-10/+10
2023-07-23accel/tcg: Take mmap_lock in load_atomic*_or_exitRichard Henderson1-14/+18
2023-07-23accel/tcg: Fix sense of read-only probes in ldst_atomicityRichard Henderson1-2/+2
2023-07-17accel/tcg: Zero-pad PC in TCG CPU exec trace linesPeter Maydell2-3/+3
2023-07-15tcg: Use HAVE_CMPXCHG128 instead of CONFIG_CMPXCHG128Richard Henderson4-4/+4
2023-07-15accel/tcg: Always lock pages before translationRichard Henderson5-134/+237
2023-07-15accel/tcg: Return bool from page_check_rangeRichard Henderson2-13/+13
2023-07-15accel/tcg: Accept more page flags in page_check_rangeRichard Henderson1-2/+2
2023-07-15accel/tcg: Introduce page_find_range_emptyRichard Henderson1-0/+41
2023-07-15accel/tcg: Introduce page_check_range_emptyRichard Henderson1-0/+7
2023-07-15accel/tcg: Split out cpu_exec_longjmp_cleanupRichard Henderson1-24/+19
2023-07-03plugins: force slow path when plugins instrument memory opsAlex Bennée2-9/+40
2023-07-01accel/tcg: Assert one page in tb_invalidate_phys_page_range__lockedMark Cave-Ayland1-0/+3
2023-07-01accel/tcg: Fix start page passed to tb_invalidate_phys_page_range__lockedMark Cave-Ayland1-4/+6
2023-06-28accel: Remove unused hThread variable on TCG/WHPXPhilippe Mathieu-Daudé2-7/+0
2023-06-26accel/tcg: Move TLB_WATCHPOINT to TLB_SLOW_FLAGS_MASKRichard Henderson1-4/+14
2023-06-26accel/tcg: Store some tlb flags in CPUTLBEntryFullRichard Henderson1-39/+57
2023-06-26accel/tcg: Remove check_tcg_memory_orders_compatibleRichard Henderson1-27/+8
2023-06-26tcg: Add host memory barriers to cpu_ldst.h interfacesRichard Henderson3-0/+54
2023-06-26accel/tcg: remove CONFIG_PROFILERFei Wu3-74/+0
2023-06-26accel/tcg: Replace target_ulong with vaddr in translator_*()Anton Johansson1-5/+5
2023-06-26accel/tcg: Replace target_ulong with vaddr in *_mmu_lookup()Anton Johansson2-6/+6
2023-06-26accel: Replace target_ulong with vaddr in probe_*()Anton Johansson2-10/+10
2023-06-26accel/tcg: Widen pc to vaddr in CPUJumpCacheAnton Johansson3-8/+8
2023-06-26accel/tcg/cpu-exec.c: Widen pc to vaddrAnton Johansson1-17/+17
2023-06-26accel/tcg/cputlb.c: Widen addr in MMULookupPageDataAnton Johansson1-15/+15
2023-06-26accel/tcg/cputlb.c: Widen CPUTLBEntry access functionsAnton Johansson1-4/+4
2023-06-26target: Widen pc/cs_base in cpu_get_tb_cpu_stateAnton Johansson2-4/+8
2023-06-26accel/tcg/translate-all.c: Widen pc and cs_baseAnton Johansson2-8/+8
2023-06-26accel: Replace target_ulong in tlb_*()Anton Johansson2-91/+88
2023-06-20accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' headerPhilippe Mathieu-Daudé1-1/+1
2023-06-20meson: Replace CONFIG_SOFTMMU -> CONFIG_SYSTEM_ONLYPhilippe Mathieu-Daudé1-3/+3
2023-06-20accel/tcg: Check for USER_ONLY definition instead of SOFTMMU onePhilippe Mathieu-Daudé2-5/+5
2023-06-20accel/tcg: Handle MO_ATOM_WITHIN16 in do_st16_leNRichard Henderson1-0/+1
2023-06-13util/log: Add vector registers to logIvan Klokov1-0/+3
2023-06-06accel/tcg: Fix undefined shift in store_whole_le16Richard Henderson1-1/+3
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