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2025-05-28tcg: Drop TCGContext.page_{mask,bits}Richard Henderson1-4/+0
Use exec/target_page.h instead of independent variables. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-28tcg: Drop TCGContext.tlb_dyn_max_bitsRichard Henderson1-2/+0
This was an extremely minor optimization for aarch64 and x86_64, to use a 32-bit AND instruction when the guest softmmu tlb maximum was sufficiently small. Both hosts can simply use a 64-bit AND insn instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-01accel/tcg: Build translate-all.c twiceRichard Henderson1-32/+0
Remove lots and lots of unused headers. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-01accel/tcg: Use target_long_bits() in translate-all.cRichard Henderson1-1/+2
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-01accel/tcg: Don't use TARGET_LONG_BITS in decode_sleb128Richard Henderson1-1/+1
When we changed decode_sleb128 from target_long to int64_t, we failed to adjust the shift limit. Cc: qemu-stable@nongnu.org Fixes: c9ad8d27caa ("tcg: Widen gen_insn_data to uint64_t") Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-05-01tcg: Define INSN_START_WORDS as constant 3Richard Henderson1-10/+9
Use the same value for all targets. Rename TARGET_INSN_START_WORDS and do not depend on TARGET_INSN_START_EXTRA_WORDS. Remove TCGContext.insn_start_words. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Pass TCGTBCPUState to tb_gen_codeRichard Henderson1-15/+13
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOpsRichard Henderson1-1/+1
Move the global function name to a hook on TCGCPUOps. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_stateRichard Henderson1-6/+2
Combine 3 different pointer returns into one structure return. Include a cflags field in TCGTBCPUState, not filled in by cpu_get_tb_cpu_state, but used by all callers. This fills a hole in the structure and is useful in some subroutines. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30include: Remove 'exec/exec-all.h'Philippe Mathieu-Daudé1-1/+0
"exec/exec-all.h" is now fully empty, let's remove it. Mechanical change running: $ sed -i '/exec\/exec-all.h/d' $(git grep -wl exec/exec-all.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mark Cave-Ayland <mark.caveayland@nutanix.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-14-philmd@linaro.org>
2025-04-30accel/tcg: Include 'accel/tcg/getpc.h' in 'exec/helper-proto'Philippe Mathieu-Daudé1-0/+1
Most files including "exec/helper-proto.h" call GETPC(). Include it there (in the common part) instead of the unspecific "exec/exec-all.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250424202412.91612-10-philmd@linaro.org>
2025-04-30accel/tcg: Merge internal-target.h into internal-common.hRichard Henderson1-1/+0
There's nothing left in internal-target.h that is target specific. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-30accel/tcg: Add CPUState arg to tb_invalidate_phys_rangeRichard Henderson1-1/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Remove use of TCG_GUEST_DEFAULT_MO in tb_gen_code()Philippe Mathieu-Daudé1-1/+1
Use TCGCPUOps::guest_default_memory_order to set TCGContext::guest_mo. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Always define TCG_GUEST_DEFAULT_MOPhilippe Mathieu-Daudé1-4/+0
We only require the TCG_GUEST_DEFAULT_MO for MTTCG-enabled frontends, otherwise we use a default value of TCG_MO_ALL. In order to simplify, require the definition for all targets, defining it for hexagon, m68k, rx, sh4 and tricore. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23tcg: Include missing 'cpu.h' in translate-all.cPhilippe Mathieu-Daudé1-0/+1
tb_check_watchpoint() calls cpu_get_tb_cpu_state(), which is declared in each "cpu.h" header. It is indirectly included via "tcg/insn-start-words.h". Since we want to rework "tcg/insn-start-words.h", removing "cpu.h" in the next commit, add the missing header now, otherwise we'd get: accel/tcg/translate-all.c:598:9: error: call to undeclared function 'cpu_get_tb_cpu_state' [-Wimplicit-function-declaration] 598 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | ^ Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23accel/tcg: fix missing includes for TCG_GUEST_DEFAULT_MOPierrick Bouvier1-0/+1
We prepare to remove cpu.h from cpu-all.h, which will transitively remove it from accel/tcg/tb-internal.h, and thus from most of tcg compilation units. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250325045915.994760-12-pierrick.bouvier@linaro.org>
2025-04-23accel/tcg: Split out tlb-bounds.hRichard Henderson1-0/+1
The CPU_TLB_DYN_{MIN,MAX}_BITS definitions are not required outside of cputlb.c and translate-all.c. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/exec: Split out icount.hRichard Henderson1-1/+1
Split icount stuff from system/cpu-timers.h. There are 17 files which only require icount.h, 7 that only require cpu-timers.h, and 7 that require both. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/system: Move exec/ram_addr.h to system/ram_addr.hRichard Henderson1-1/+1
Convert the existing includes with sed. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-04-23include/exec: Split out mmap-lock.hRichard Henderson1-0/+1
Split out mmap_lock, et al from page-protection.h to a new header. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2025-03-09accel: Prefer cached CpuClass over CPU_GET_CLASS() macroPhilippe Mathieu-Daudé1-1/+1
CpuState caches its CPUClass since commit 6fbdff87062 ("cpu: cache CPUClass in CPUState for hot code paths"), use it. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250122093028.52416-6-philmd@linaro.org>
2025-03-06accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h'Philippe Mathieu-Daudé1-1/+0
The heavily imported "system/cpus.h" header includes "accel-ops.h" to get AccelOpsClass type declaration. Reduce headers pressure by forward declaring it in "qemu/typedefs.h", where we already declare the AccelCPUState type. Reduce "system/cpus.h" inclusions by only including "system/accel-ops.h" when necessary. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-14-philmd@linaro.org>
2025-03-06accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h'Philippe Mathieu-Daudé1-1/+1
TCGCPUOps structure makes more sense in the accelerator context rather than hardware emulation. Move it under the accel/tcg/ scope. Mechanical change doing: $ sed -i -e 's,hw/core/tcg-cpu-ops.h,accel/tcg/cpu-ops.h,g' \ $(git grep -l hw/core/tcg-cpu-ops.h) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20250123234415.59850-11-philmd@linaro.org>
2025-01-21Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi1-9/+18
tcg: - Add TCGOP_TYPE, TCGOP_FLAGS. - Pass type and flags to tcg_op_supported, tcg_target_op_def. - Split out tcg-target-has.h and unexport from tcg.h. - Reorg constraint processing; constify TCGOpDef. - Make extract, sextract, deposit opcodes mandatory. - Merge ext{8,16,32}{s,u} opcodes into {s}extract. tcg/mips: Expand bswap unconditionally tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv: Use BEXTI for single-bit extractions tcg/sparc64: Use SRA, SRL for {s}extract_i64 disas/riscv: Guard dec->cfg dereference for host disassemble util/cpuinfo-riscv: Detect Zbs accel/tcg: Call tcg_tb_insert() for one-insn TBs linux-user: Add missing /proc/cpuinfo fields for sparc # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmeKnzUdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+Kvgf+LG9UjXlWF9GK923E # TllBL2rLf1OOdtTXWO15VcvGMoWDwB3tVBdhihdvXmnWju+WbfMk6mct5NhzsKn9 # LmuugMIZs+hMROj+bgMK8x47jRIh5N2rDYxcEgmyfIpYb2o9qvyqKecGVRlSJTCE # bmt5UFbvPThBb8upoMfq3F6evuMx0szBP7wrOwSR/VGpmzIr20UTEWo6I1ALp4uj # paFaysYol4em3dIhkiuV9cL7E0EIObaNa7l9RUci/BmTq+JaVxUnW1Y2i0PEwKwG # FJSfYTJk3wBgAVxC2zC2g3ZM7uKuecSXMpiFopTiuyQLp7Q61i9kCNvEq0qY5tdb # DaqR/g== # =cv4O # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Jan 2025 13:19:33 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits) softfloat: Constify helpers returning float_status field accel/tcg: Call tcg_tb_insert() for one-insn TBs tcg: Document tb_lookup() and tcg_tb_lookup() linux-user: Add missing /proc/cpuinfo fields for sparc tcg/riscv: Use BEXTI for single-bit extractions util/cpuinfo-riscv: Detect Zbs tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64} tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64} tcg/tci: Remove assertions for deposit and extract tcg/tci: Provide TCG_TARGET_{s}extract_valid tcg/sparc64: Use SRA, SRL for {s}extract_i64 tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64 tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract tcg/arm: Add full [US]XT[BH] into {s}extract tcg/aarch64: Expand extract with offset 0 with andi tcg/aarch64: Provide TCG_TARGET_{s}extract_valid ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-01-17accel/tcg: Call tcg_tb_insert() for one-insn TBsIlya Leoshkevich1-9/+18
Currently one-insn TBs created from I/O memory are not added to region_trees. Therefore, when they generate exceptions, they are not handled by cpu_restore_state_from_tb(). For x86 this is not a problem, because x86_restore_state_to_opc() only restores pc and cc, which already have the correct values if the first TB instruction causes an exception. However, on several other architectures, restore_state_to_opc() is not stricly limited to state restoration and affects some exception-related registers, where guests can notice incorrect values, for example: - arm's exception.syndrome; - hppa's unwind_breg; - riscv's excp_uw2; - s390x's int_pgm_ilen. Fix by always calling tcg_tb_insert(). This may increase the size of region_trees, but tcg_region_reset_all() clears it once code_gen_buffer fills up, so it will not grow uncontrollably. Do not call tb_link_page(), which would add such TBs to the QHT, to prevent tb_lookup() from finding them. These TBs are single-use, since subsequent reads from I/O memory may return different values; they are not removed from code_gen_buffer only in order to keep things simple. Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250116213214.5695-2-iii@linux.ibm.com>
2025-01-17accel/tcg: also suppress asynchronous IRQs for cpu_io_recompileAlex Bennée1-2/+3
While it would be technically correct to allow an IRQ to happen (as the offending instruction never really completed) it messes up instrumentation. We already take care to only use memory instrumentation on the block, we should also suppress IRQs. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Julian Ganz <neither@nut.email> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20250116160306.1709518-23-alex.bennee@linaro.org>
2024-12-24accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_coreRichard Henderson1-3/+5
Convert all targets simultaneously, as the gen_intermediate_code function disappears from the target. While there are possible workarounds, they're larger than simply performing the conversion. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-12-20accel/tcg: Move TranslationBlock declarations to 'tb-internal.h'Philippe Mathieu-Daudé1-0/+1
Move declarations related to TranslationBlock out of the generic "internal-target.h" to "tb-internal.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-11-philmd@linaro.org>
2024-12-20accel/tcg: Move 'exec/translate-all.h' -> 'tb-internal.h'Philippe Mathieu-Daudé1-1/+1
"exec/translate-all.h" is only useful to TCG accelerator, so move it to accel/tcg/, after renaming it 'tb-internal.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-9-philmd@linaro.org>
2024-12-20accel/tcg: Declare mmap_[un]lock() in 'exec/page-protection.h'Philippe Mathieu-Daudé1-0/+1
Move mmap_lock(), mmap_unlock() declarations and the WITH_MMAP_LOCK_GUARD() definition to 'exec/page-protection.h'. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20241212185341.2857-5-philmd@linaro.org>
2024-12-20include: Rename sysemu/ -> system/Philippe Mathieu-Daudé1-3/+3
Headers in include/sysemu/ are not only related to system *emulation*, they are also used by virtualization. Rename as system/ which is clearer. Files renamed manually then mechanical change using sed tool. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Lei Yang <leiyang@redhat.com> Message-Id: <20241203172445.28576-1-philmd@linaro.org>
2024-05-06accel/tcg: Move user definition of cpu_interrupt() to user-exec.cPhilippe Mathieu-Daudé1-9/+0
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20240428221450.26460-4-philmd@linaro.org>
2024-03-29accel/tcg: Use CPUState.get_pc in cpu_io_recompileRichard Henderson1-1/+1
Using log_pc produces the pc at the beginning of TB, not the actual pc installed by cpu_restore_state_from_tb, which could be any of the guest instructions within TB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-02-29cpu: Remove page_size_initRichard Henderson1-1/+0
Move qemu_host_page_{size,mask} and HOST_PAGE_ALIGN into bsd-user. It should be removed from bsd-user as well, but defer that cleanup. Reviewed-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20240102015808.132373-28-richard.henderson@linaro.org>
2024-01-29accel/tcg: Move perf and debuginfo support to tcg/Ilya Leoshkevich1-1/+1
tcg/ should not depend on accel/tcg/, but perf and debuginfo support provided by the latter are being used by tcg/tcg.c. Since that's the only user, move both to tcg/. Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20231212003837.64090-5-iii@linux.ibm.com> Message-Id: <20240125054631.78867-5-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-01-08system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()Stefan Hajnoczi1-1/+1
The Big QEMU Lock (BQL) has many names and they are confusing. The actual QemuMutex variable is called qemu_global_mutex but it's commonly referred to as the BQL in discussions and some code comments. The locking APIs, however, are called qemu_mutex_lock_iothread() and qemu_mutex_unlock_iothread(). The "iothread" name is historic and comes from when the main thread was split into into KVM vcpu threads and the "iothread" (now called the main loop thread). I have contributed to the confusion myself by introducing a separate --object iothread, a separate concept unrelated to the BQL. The "iothread" name is no longer appropriate for the BQL. Rename the locking APIs to: - void bql_lock(void) - void bql_unlock(void) - bool bql_locked(void) There are more APIs with "iothread" in their names. Subsequent patches will rename them. There are also comments and documentation that will be updated in later patches. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Paul Durrant <paul@xen.org> Acked-by: Fabiano Rosas <farosas@suse.de> Acked-by: David Woodhouse <dwmw@amazon.co.uk> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: Peter Xu <peterx@redhat.com> Acked-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Acked-by: Hyman Huang <yong.huang@smartx.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-id: 20240102153529.486531-2-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-14accel/tcg: Remove CF_LAST_IORichard Henderson1-2/+2
In cpu_exec_step_atomic, we did not set CF_LAST_IO, which lead to a loop with cpu_io_recompile. But since 18a536f1f8 ("Always require can_do_io") we no longer need a flag to indicate when the last insn should have can_do_io set, so remove the flag entirely. Reported-by: Clément Chigot <chigot@adacore.com> Tested-by: Clément Chigot <chigot@adacore.com> Reviewed-by: Claudio Fontana <cfontana@suse.de> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1961 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-07accel/tcg: Factor tcg_cpu_reset_hold() outPhilippe Mathieu-Daudé1-8/+0
Factor the TCG specific code from cpu_common_reset_hold() to tcg_cpu_reset_hold() within tcg-accel-ops.c. Since this file is sysemu specific, we can inline tcg_flush_softmmu_tlb(), removing its declaration in "exec/cpu-common.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230918104153.24433-4-philmd@linaro.org>
2023-11-06accel/tcg: Move HMP info jit and info opcount codeRichard Henderson1-127/+0
Move all of it into accel/tcg/monitor.c. This puts everything about tcg that is only used by the monitor in the same place. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04accel/tcg: Make monitor.c a target-agnostic unitPhilippe Mathieu-Daudé1-0/+1
Move target-agnostic declarations from "internal-target.h" to a new "internal-common.h" header. monitor.c now don't include target specific headers and can be compiled once in system_ss[]. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230914185718.76241-10-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04accel/tcg: Rename target-specific 'internal.h' -> 'internal-target.h'Philippe Mathieu-Daudé1-1/+1
accel/tcg/internal.h contains target specific declarations. Unit files including it become "target tainted": they can not be compiled as target agnostic. Rename using the '-target' suffix to make this explicit. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230914185718.76241-9-philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04tcg: Remove TCGContext.tlb_fast_offsetRichard Henderson1-2/+0
Now that there is no padding between CPUNegativeOffsetState and CPUArchState, this value is constant across all targets. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-04accel/tcg: Replace CPUState.env_ptr with cpu_env()Richard Henderson1-2/+2
Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-03accel/tcg: Remove cpu_neg()Richard Henderson1-3/+3
Now that CPUNegativeOffsetState is part of CPUState, we can reference it directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-10-03accel/tcg: Move CPUNegativeOffsetState into CPUStateRichard Henderson1-2/+2
Retain the separate structure to emphasize its importance. Enforce CPUArchState always follows CPUState without padding. Reviewed-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-31accel/tcg: Clear tcg_ctx->gen_tb on buffer overflowRichard Henderson1-0/+1
On overflow of code_gen_buffer, we unlock the guest pages we had been translating, but failed to clear gen_tb. On restart, if we cannot allocate a TB, we exit to the main loop to perform the flush of all TBs as soon as possible. With garbage in gen_tb, we hit an assert: ../src/accel/tcg/tb-maint.c:348:page_unlock__debug: \ assertion failed: (page_is_locked(pd)) Fixes: deba78709ae8 ("accel/tcg: Always lock pages before translation") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-07-17accel/tcg: Zero-pad PC in TCG CPU exec trace linesPeter Maydell1-1/+1
In commit f0a08b0913befbd we changed the type of the PC from target_ulong to vaddr. In doing so we inadvertently dropped the zero-padding on the PC in trace lines (the second item inside the [] in these lines). They used to look like this on AArch64, for instance: Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000] and now they look like this: Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000] and if the PC happens to be somewhere low like 0x5000 then the field is shown as /5000/. This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier, depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64 with no width specifier. Restore the zero-padding by adding an 016 width specifier to this tracing and a couple of others that were similarly recently changed to use VADDR_PRIx without a width specifier. We can't unfortunately restore the "32-bit guests are padded to 8 hex digits and 64-bit guests to 16 hex digits" behaviour so easily. Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
2023-07-15accel/tcg: Always lock pages before translationRichard Henderson1-5/+38
We had done this for user-mode by invoking page_protect within the translator loop. Extend this to handle system mode as well. Move page locking out of tb_link_page. Reported-by: Liren Wei <lrwei@bupt.edu.cn> Reported-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Richard W.M. Jones <rjones@redhat.com>
2023-06-26accel/tcg: remove CONFIG_PROFILERFei Wu1-33/+0
TBStats will be introduced to replace CONFIG_PROFILER totally, here remove all CONFIG_PROFILER related stuffs first. Signed-off-by: Vanderson M. do Rosario <vandersonmr2@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Fei Wu <fei2.wu@intel.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230607122411.3394702-2-fei2.wu@intel.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>