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path: root/accel/tcg/cputlb.c
AgeCommit message (Expand)AuthorFilesLines
2023-03-05accel/tcg: Trigger watchpoints from atomic_mmu_lookupRichard Henderson1-11/+29
2023-03-05accel/tcg: Honor TLB_DISCARD_WRITE in atomic_mmu_lookupRichard Henderson1-1/+1
2023-03-05accel/tcg: Retain prot flags from tlb_fillRichard Henderson1-1/+0
2023-02-28accel/tcg: Add 'size' param to probe_access_fullRichard Henderson1-2/+2
2023-02-28accel/tcg: Add 'size' param to probe_access_flags()Daniel Henrique Barboza1-3/+14
2023-02-04tcg: Add guest load/store primitives for TCGv_i128Richard Henderson1-0/+112
2023-02-04accel/tcg: Test CPUJumpCache in tb_jmp_cache_clear_pageEric Auger1-1/+6
2023-01-18bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plxPhilippe Mathieu-Daudé1-1/+1
2023-01-04accel/tcg: Use QEMU_IOTHREAD_LOCK_GUARD in io_readx/io_writexRichard Henderson1-17/+8
2022-12-20accel/tcg: Factor tb_invalidate_phys_range_fast() outPhilippe Mathieu-Daudé1-4/+1
2022-12-20accel/tcg: Rename tb_invalidate_phys_page_fast{,__locked}()Philippe Mathieu-Daudé1-1/+1
2022-12-20accel/tcg: Remove trace events from trace-root.hPhilippe Mathieu-Daudé1-1/+1
2022-10-04include/hw/core: Create struct CPUJumpCacheRichard Henderson1-4/+5
2022-10-04accel/tcg: Inline tb_flush_jmp_cacheRichard Henderson1-11/+14
2022-10-04accel/tcg: Do not align tb->page_addr[0]Richard Henderson1-1/+2
2022-10-03accel/tcg: Introduce tlb_set_page_fullRichard Henderson1-18/+33
2022-10-03accel/tcg: Introduce probe_access_fullRichard Henderson1-18/+29
2022-10-03accel/tcg: Suppress auto-invalidate in probe_access_internalRichard Henderson1-1/+9
2022-10-03accel/tcg: Drop addr member from SavedIOTLBRichard Henderson1-4/+3
2022-10-03accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFullRichard Henderson1-50/+52
2022-10-03cputlb: used cached CPUClass in our hot-pathsAlex Bennée1-9/+6
2022-09-06accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostpRichard Henderson1-50/+26
2022-09-06accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.cRichard Henderson1-12/+0
2022-09-06accel/tcg: Properly implement get_page_addr_code for user-onlyRichard Henderson1-5/+0
2022-07-12accel/tcg: Fix unaligned stores to s390x low-address-protected lowcoreIlya Leoshkevich1-3/+5
2022-04-26accel/tcg: Assert mmu_idx in range before use in cputlbRichard Henderson1-13/+27
2022-04-20accel/tcg: Remove ATOMIC_MMU_IDXRichard Henderson1-1/+0
2022-03-16accel/tcg: Fix cpu_ldq_be_mmu typoRichard Henderson1-1/+1
2022-02-14Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220211' into...Peter Maydell1-0/+9
2022-02-09tracing: remove TCG memory access tracingAlex Bennée1-2/+0
2022-02-09accel/tcg: Optimize jump cache flush during tlb range flushIdan Horowitz1-0/+9
2022-01-08exec/memop: Adding signedness to quad definitionsFrédéric Pétrot1-15/+15
2021-10-13tcg: Move helper_*_mmu decls to tcg/tcg-ldst.hRichard Henderson1-0/+1
2021-10-13accel/tcg: Add cpu_{ld,st}*_mmu interfacesRichard Henderson1-266/+126
2021-10-05trace: Split guest_mem_beforeRichard Henderson1-5/+2
2021-10-05plugins: Reorg arguments to qemu_plugin_vcpu_mem_cbRichard Henderson1-2/+2
2021-10-05trace/mem: Pass MemOpIdx to trace_mem_get_infoRichard Henderson1-8/+4
2021-10-05tcg: Rename TCGMemOpIdx to MemOpIdxRichard Henderson1-39/+39
2021-10-05accel/tcg: Drop signness in tracing in cputlb.cRichard Henderson1-7/+3
2021-07-21accel/tcg: Expand ATOMIC_MMU_LOOKUP_*Richard Henderson1-6/+1
2021-07-21accel/tcg: Remove ATOMIC_MMU_DECLSRichard Henderson1-1/+0
2021-07-21accel/tcg: Fold EXTRA_ARGS into atomic_template.hRichard Henderson1-1/+0
2021-07-21accel/tcg: Standardize atomic helpers on softmmu apiRichard Henderson1-32/+0
2021-07-21tcg: Rename helper_atomic_*_mmu and provide for user-onlyRichard Henderson1-3/+5
2021-07-14plugins: fix-up handling of internal hostaddr for 32 bitAlex Bennée1-1/+1
2021-06-19accel/tcg: Probe the proper permissions for atomic opsRichard Henderson1-29/+66
2021-05-26accel/tcg: Keep TranslationBlock headers local to TCGPhilippe Mathieu-Daudé1-1/+1
2021-05-25accel/tlb: Rename tlb_flush_[page_bits > range]_by_mmuidx_async_[2 > 1]Richard Henderson1-6/+6
2021-05-25accel/tcg: Rename tlb_flush_page_bits -> range]_by_mmuidx_async_0Richard Henderson1-6/+5
2021-05-25accel/tlb: Add tlb_flush_range_by_mmuidx_all_cpus_synced()Richard Henderson1-7/+20
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