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2024-04-30Merge tag 'pull-target-arm-20240430' of ↵Richard Henderson33-123/+986
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/core/clock: allow clock_propagate on child clocks * hvf: arm: Remove unused PL1_WRITE_MASK define * target/arm: Restrict translation disabled alignment check to VMSA * docs/system/arm/emulation.rst: Add missing implemented features * target/arm: Enable FEAT_CSV2_3, FEAT_ETS2, FEAT_Spec_FPACC for 'max' * tests/avocado: update sunxi kernel from armbian to 6.6.16 * target/arm: Make new CPUs default to 1GHz generic timer * hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields * hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size * hw/arm/npcm7xx: Store derivative OTP fuse key in little endian * hw/arm: Add DM163 display to B-L475E-IOT01A board # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmYxILcZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3pRzD/40UZrhNbS+FEANkXJ7qpUm # giCKn8hVwteWY4T4LugUK9987lU0HZ7CGfsHoSaWNwa7RBdKUoDRqi/CQ1kCfeDO # XET42do+6SJhak+4wmzEfYD+K7wnlauun0/dyqCjd2+JP0bln/MIY5r8JCN1GiYS # YSAAKoZqAfG1bC3HmxELI9min09GPT+tzw0PAyVJipRtfE+ykZXoCytu0GWU5jB+ # VBI6SGmqMPd/c/7JfJV8KP8R0Mn3etA3hbOCx7YDL6cUmbepWtNPV8dLeTwofrpa # 01uqN83PpbbSYr96QdXXa7Ov105hQH7e8jmr9+7jTpd3f9U7+GwsxxqDR1KDHLgn # pUGZneoTDTkJugfXM28A0VoVB3eyJYPCLE9QQ/HXpChXc62NOQV5jcECgLiUDujH # hVbeGEG0KViQlhMUfI3vIfTaIjEALDcNw5bxVUCqg8vdO6UtTXqqWdaS4Xgne8HB # KeCu5xXngXEZjIgidZkmIC15FD60B19JdQz2WR+6BDCw8Ajm9iPWlj+ftZztuX/S # cFSUZ05BPbTkBzAHG4GBvjXTdwsxX2acGBNtdETOQAxhkoRcug0Pn+BmrZQLqkm5 # mPKPW9FFxIkkgeK/ZdA4uIEwDZX/LQlnrX129XGt7DVr+yDNKekaVGfLL8x8alT1 # 3v0Ni/nntc6QtZDB88OIzA== # =vAf/ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Apr 2024 09:47:51 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] * tag 'pull-target-arm-20240430' of https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits) tests/qtest : Add testcase for DM163 hw/arm : Connect DM163 to B-L475E-IOT01A hw/arm : Create Bl475eMachineState hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoC hw/display : Add device DM163 hw/arm/npcm7xx: Store derivative OTP fuse key in little endian hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fields target/arm: Default to 1GHz cntfrq for 'max' and new CPUs hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM property hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz target/arm: Refactor default generic timer frequency handling tests/avocado: update sunxi kernel from armbian to 6.6.16 target/arm: Enable FEAT_Spec_FPACC for -cpu max target/arm: Implement ID_AA64MMFR3_EL1 target/arm: Enable FEAT_ETS2 for -cpu max target/arm: Enable FEAT_CSV2_3 for -cpu max docs/system/arm/emulation.rst: Add missing implemented features target/arm: Restrict translation disabled alignment check to VMSA hvf: arm: Remove PL1_WRITE_MASK ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30Merge tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu into ↵Richard Henderson15-148/+149
staging * Clean-ups for "errp" handling in s390x cpu_model code * Fix a possible abort in the "edu" device * Add missing qga stubs for stand-alone qga builds and re-enable qga-ssh-test * Fix memory corruption caused by the stm32l4x5 uart device * Update the s390x custom runner to Ubuntu 22.04 * Fix READ NATIVE MAX ADDRESS IDE commands to avoid a possible crash * Shorten the runtime of Cirrus-CI jobs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmYwmaMRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUCERAAss5PJMG8rI4i4X/3nW49JYTlPOpgm/YX # /UWF+eHUlqaqDdE0s+Pdw4Ozo3hXQt/E/CkcyflUTzVpnZtpv9vkhNWyjOoPV31v # GQyQEzGvxZXl2S595XefyAyaMTP5maBhUTlyZWJo385cQraa60Ot5d4Mibr2CobY # gIBRxEGB/frJYpbHJPxd/FxJV120gtuWAdZwGGYYYjwMzf2IKu2veODB8CnUErlX # WNUsIzjtAslfh8Ek2ZmPzD7uktCUeigkukqIrLC1oEU3wzbJHkISv1kXCKPW/Nf6 # ISjVa5TqGwkiiF8fw9aYKvWrnPJS7JkhXw7Gz+b39d846kUdNyDfgLcYJeNS3cZ2 # R1xgR9B6hX8ZmikMbGC+0/Sv15u2Yr+bFxJBTJzq6zdOAb9EJNQY1hW2w/Lbrg3X # LjY+ltcVweoSILT6AE6vGDPCHfBzO+6FcptFvw7ePvRGOlwAPZ3tEB9G2LEbCYgg # BjWNP4aRuSfbUebO4x4Todz65WN8aY1EIBXORU/wgUlF2+zajWiOI5JRDKjWz2qQ # gAMeCbLplli5bYrChWtouRIXtb061cQloULddu/SRFcaJOlV3SCzx4JfN15pU90s # jRMIhMESAEj4NSfclhxsOiYp3ywZTvlQsVA6MgPlu2i3HJakQnt5zbg59TesRn2d # r5PfAk83UnA= # =0OB7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 30 Apr 2024 12:11:31 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] * tag 'pull-request-2024-04-30' of https://gitlab.com/thuth/qemu: .gitlab-ci.d/cirrus: Remove the netbsd and openbsd jobs .gitlab-ci.d/cirrus.yml: Shorten the runtime of the macOS and FreeBSD jobs tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limited hw/ide/core.c (cmd_read_native_max): Avoid limited device parameters gitlab: remove stale s390x-all-linux-static conf hacks gitlab: migrate the s390x custom machine to 22.04 build-environment: make some packages optional hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_size qga: Re-enable the qga-ssh-test when running without fuzzing stubs: Add missing qga stubs hw: misc: edu: use qemu_log_mask instead of hw_error hw: misc: edu: rename local vars in edu_check_range hw: misc: edu: fix 2 off-by-one errors target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model() target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return boolean target/s390x/cpu_models: Drop local @err in get_max_cpu_model() target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return boolean target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model() target/s390x/cpu_model: Make check_compatibility() return boolean Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30tests/qtest : Add testcase for DM163Inès Varhol2-0/+196
`test_dm163_bank()` Checks that the pin "sout" of the DM163 led driver outputs the values received on pin "sin" with the expected latency (depending on the bank). `test_dm163_gpio_connection()` Check that changes to relevant STM32L4x5 GPIO pins are propagated to the DM163 device. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-6-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm : Connect DM163 to B-L475E-IOT01AInès Varhol2-2/+58
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-5-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm : Create Bl475eMachineStateInès Varhol1-14/+32
Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-4-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm : Pass STM32L4x5 SYSCFG gpios to STM32L4x5 SoCInès Varhol3-14/+22
Exposing SYSCFG inputs to the SoC is practical in order to wire the SoC to the optional DM163 display from the board code (GPIOs outputs need to be connected to both SYSCFG inputs and DM163 inputs). STM32L4x5 SYSCFG in-irq interception needed to be changed accordingly. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-3-ines.varhol@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/display : Add device DM163Inès Varhol6-1/+428
This device implements the IM120417002 colors shield v1.1 for Arduino (which relies on the DM163 8x3-channel led driving logic) and features a simple display of an 8x8 RGB matrix. The columns of the matrix are driven by the DM163 and the rows are driven externally. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240424200929.240921-2-ines.varhol@telecom-paris.fr [PMM: updated to new reset hold method prototype] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/arm/npcm7xx: Store derivative OTP fuse key in little endianPhilippe Mathieu-Daudé1-1/+2
Use little endian for derivative OTP fuse key. Cc: qemu-stable@nongnu.org Fixes: c752bb079b ("hw/nvram: NPCM7xx OTP device model") Suggested-by: Avi Fishman <Avi.Fishman@nuvoton.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240422125813.1403-1-philmd@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_sizeThomas Huth1-0/+1
"make check-qtest-aarch64" recently started failing on FreeBSD builds, and valgrind on Linux also detected that there is something fishy with the new stm32l4x5-usart: The code forgot to set the correct class_size here, so the various class_init functions in this file wrote beyond the allocated buffer when setting the subc->type field. Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton") Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240429075908.36302-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/dmax/xlnx_dpdma: fix handling of address_extension descriptor fieldsAlexandra Diupina1-10/+10
The DMA descriptor structures for this device have a set of "address extension" fields which extend the 32 bit source addresses with an extra 16 bits to give a 48 bit address: https://docs.amd.com/r/en-US/ug1085-zynq-ultrascale-trm/ADDR_EXT-Field However, we misimplemented this address extension in several ways: * we only extracted 12 bits of the extension fields, not 16 * we didn't shift the extension field up far enough * we accidentally did the shift as 32-bit arithmetic, which meant that we would have an overflow instead of setting bits [47:32] of the resulting 64-bit address Add a type cast and use extract64() instead of extract32() to avoid integer overflow on addition. Fix bit fields extraction according to documentation. Found by Linux Verification Center (linuxtesting.org) with SVACE. Cc: qemu-stable@nongnu.org Fixes: d3c6369a96 ("introduce xlnx-dpdma") Signed-off-by: Alexandra Diupina <adiupina@astralinux.ru> Message-id: 20240428181131.23801-1-adiupina@astralinux.ru [PMM: adjusted commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30Merge tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu into ↵Richard Henderson8-162/+670
staging Add boot LoongArch elf kernel with FDT v2: Fix 'make check-tcg' fail. # -----BEGIN PGP SIGNATURE----- # # iLMEAAEKAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZi8F3AAKCRBAov/yOSY+ # 35VrBADb6f1mYNUTG5iDvKppvA8RG1TybxfXfgA+Z9vPkJqFkT6wt8J+JFwgh3UT # w0xY2Y2xZkPjxnUpEhZiVJjp5hk+BEzr3vE4M5DzKC1vpCYpbojxxN6FB41Up862 # kS7slW6XsZgKpLLvUkFttPt3G4DUN29CscVgy4Ci0zrqyNjnsw== # =ufbc # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Apr 2024 07:28:44 PM PDT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20240429' of https://gitlab.com/gaosong/qemu: hw/loongarch: Add cells missing from rtc node hw/loongarch: Add cells missing from uart node hw/loongarch: fdt remove unused irqchip node hw/loongarch: fdt adds pcie irq_map node hw/loongarch: fdt adds pch_msi Controller hw/loongarch: fdt adds pch_pic Controller hw/loongarch: fdt adds Extend I/O Interrupt Controller hw/loongarch: fdt adds cpu interrupt controller node hw/loongarch: Fix fdt memory node wrong 'reg' hw/loongarch: Init efi_fdt table hw/loongarch: Init efi_initrd table hw/loongarch: Init efi_boot_memmap table hw/loongarch: Init efi_system_table hw/loongarch: Add init_cmdline hw/loongarch: Add slave cpu boot_code hw/loongarch: Add load initrd hw/loongarch: Move boot functions to boot.c Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-30target/arm: Default to 1GHz cntfrq for 'max' and new CPUsPeter Maydell7-9/+65
In previous versions of the Arm architecture, the frequency of the generic timers as reported in CNTFRQ_EL0 could be any IMPDEF value, and for QEMU we picked 62.5MHz, giving a timer tick period of 16ns. In Armv8.6, the architecture standardized this frequency to 1GHz. Because there is no ID register feature field that indicates whether a CPU is v8.6 or that it ought to have this counter frequency, we implement this by changing our default CNTFRQ value for all CPUs, with exceptions for backwards compatibility: * CPU types which we already implement will retain the old default value. None of these are v8.6 CPUs, so this is architecturally OK. * CPUs used in versioned machine types with a version of 9.0 or earlier will retain the old default value. The upshot is that the only CPU type that changes is 'max'; but any new type we add in future (whether v8.6 or not) will also get the new 1GHz default. It remains the case that the machine model can override the default value via the 'cntfrq' QOM property (regardless of the CPU type). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-5-peter.maydell@linaro.org
2024-04-30hw/watchdog/sbsa_gwdt: Make watchdog timer frequency a QOM propertyPeter Maydell3-3/+16
Currently the sbsa_gdwt watchdog device hardcodes its frequency at 62.5MHz. In real hardware, this watchdog is supposed to be driven from the system counter, which also drives the CPU generic timers. Newer CPU types (in particular from Armv8.6) should have a CPU generic timer frequency of 1GHz, so we can't leave the watchdog on the old QEMU default of 62.5GHz. Make the frequency a QOM property so it can be set by the board, and have our only board that uses this device set that frequency to the same value it sets the CPU frequency. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240426122913.3427983-4-peter.maydell@linaro.org
2024-04-30hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHzPeter Maydell1-0/+15
Currently QEMU CPUs always run with a generic timer counter frequency of 62.5MHz, but ARMv8.6 CPUs will run at 1GHz. For older versions of the TF-A firmware that sbsa-ref runs, the frequency of the generic timer is hardcoded into the firmware, and so if the CPU actually has a different frequency then timers in the guest will be set incorrectly. The default frequency used by the 'max' CPU is about to change, so make the sbsa-ref board force the CPU frequency to the value which the firmware expects. Newer versions of TF-A will read the frequency from the CPU's CNTFRQ_EL0 register: https://github.com/ARM-software/arm-trusted-firmware/commit/4c77fac98dac0bebc63798aae9101ac865b87148 so in the longer term we could make this board use the 1GHz frequency. We will need to make sure we update the binaries used by our avocado test Aarch64SbsarefMachine.test_sbsaref_alpine_linux_max_pauth_impdef before we can do that. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Message-id: 20240426122913.3427983-3-peter.maydell@linaro.org
2024-04-30target/arm: Refactor default generic timer frequency handlingPeter Maydell3-25/+29
The generic timer frequency is settable by board code via a QOM property "cntfrq", but otherwise defaults to 62.5MHz. The way this is done includes some complication resulting from how this was originally a fixed value with no QOM property. Clean it up: * always set cpu->gt_cntfrq_hz to some sensible value, whether the CPU has the generic timer or not, and whether it's system or user-only emulation * this means we can always use gt_cntfrq_hz, and never need the old GTIMER_SCALE define * set the default value in exactly one place, in the realize fn The aim here is to pave the way for handling the ARMv8.6 requirement that the generic timer frequency is always 1GHz. We're going to do that by having old CPU types keep their legacy-in-QEMU behaviour and having the default for any new CPU types be a 1GHz rather han 62.5MHz cntfrq, so we want the point where the default is decided to be in one place, and in code, not in a DEFINE_PROP_UINT64() initializer. This commit should have no behavioural changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240426122913.3427983-2-peter.maydell@linaro.org
2024-04-30tests/avocado: update sunxi kernel from armbian to 6.6.16Peter Maydell2-39/+39
The Linux kernel 5.10.16 binary for sunxi has been removed from apt.armbian.com. This means that the avocado tests for these machines will be skipped (status CANCEL) if the old binary isn't present in the avocado cache. Update to 6.6.16, in the same way we did in commit e384db41d8661 when we moved to 5.10.16 in 2021. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2284 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com> Message-id: 20240415151845.1564201-1-peter.maydell@linaro.org
2024-04-30target/arm: Enable FEAT_Spec_FPACC for -cpu maxPeter Maydell2-0/+5
FEAT_Spec_FPACC is a feature describing speculative behaviour in the event of a PAC authontication failure when FEAT_FPACCOMBINE is implemented. FEAT_Spec_FPACC means that the speculative use of pointers processed by a PAC Authentication is not materially different in terms of the impact on cached microarchitectural state (caches, TLBs, etc) between passing and failing of the PAC Authentication. QEMU doesn't do speculative execution, so we can advertise this feature. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-6-peter.maydell@linaro.org
2024-04-30target/arm: Implement ID_AA64MMFR3_EL1Peter Maydell4-2/+25
Newer versions of the Arm ARM (e.g. rev K.a) now define fields for ID_AA64MMFR3_EL1. Implement this register, so that we can set the fields if we need to. There's no behaviour change here since we don't currently set the register value to non-zero. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-5-peter.maydell@linaro.org
2024-04-30target/arm: Enable FEAT_ETS2 for -cpu maxPeter Maydell3-3/+3
FEAT_ETS2 is a tighter set of guarantees about memory ordering involving translation table walks than the old FEAT_ETS; FEAT_ETS has been retired from the Arm ARM and the old ID_AA64MMFR1.ETS == 1 now gives no greater guarantees than ETS == 0. FEAT_ETS2 requires: * the virtual address of a load or store that appears in program order after a DSB cannot be translated until after the DSB completes (section B2.10.9) * TLB maintenance operations that only affect translations without execute permission are guaranteed complete after a DSB (R_BLDZX) * if a memory access RW2 is ordered-before memory access RW2, then RW1 is also ordered-before any translation table walk generated by RW2 that generates a Translation, Address size or Access flag fault (R_NNFPF, I_CLGHP) As with FEAT_ETS, QEMU is already compliant, because we do not reorder translation table walk memory accesses relative to other memory accesses, and we always guarantee to have finished TLB maintenance as soon as the TLB op is done. Update the documentation to list FEAT_ETS2 instead of the no-longer-existent FEAT_ETS, and update the 'max' CPU ID registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-4-peter.maydell@linaro.org
2024-04-30target/arm: Enable FEAT_CSV2_3 for -cpu maxPeter Maydell2-2/+3
FEAT_CSV2_3 adds a mechanism to identify if hardware cannot disclose information about whether branch targets and branch history trained in one hardware described context can control speculative execution in a different hardware context. There is no branch prediction in TCG, so we don't need to do anything to be compliant with this. Upadte the '-cpu max' ID registers to advertise the feature. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20240418152004.2106516-3-peter.maydell@linaro.org
2024-04-30docs/system/arm/emulation.rst: Add missing implemented featuresPeter Maydell1-2/+36
As of version DDI0487K.a of the Arm ARM, some architectural features which previously didn't have official names have been named. Add these to the list of features which QEMU's TCG emulation supports. Mostly these are features which we thought of as part of baseline 8.0 support. For SVE and SVE2, the names have been brought into line with the FEAT_* naming convention of other extensions, and some sub-components split into separate FEAT_ items. In a few cases (eg FEAT_CCIDX, FEAT_DPB2) the omission from our list was just an oversight. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240418152004.2106516-2-peter.maydell@linaro.org
2024-04-30target/arm: Restrict translation disabled alignment check to VMSARichard Henderson1-2/+10
For cpus using PMSA, when the MPU is disabled, the default memory type is Normal, Non-cachable. This means that it should not have alignment restrictions enforced. Cc: qemu-stable@nongnu.org Fixes: 59754f85ed3 ("target/arm: Do memory type alignment check when translation disabled") Reported-by: Clément Chigot <chigot@adacore.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Clément Chigot <chigot@adacore.com> Message-id: 20240422170722.117409-1-richard.henderson@linaro.org [PMM: trivial comment, commit message tweaks] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hvf: arm: Remove PL1_WRITE_MASKZenghui Yu1-1/+0
As it had never been used since the first commit a1477da3ddeb ("hvf: Add Apple Silicon support"). Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Message-id: 20240422092715.71973-1-zenghui.yu@linux.dev Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30hw/core/clock: allow clock_propagate on child clocksRaphael Poggi1-1/+0
clock_propagate() has an assert that clk->source is NULL, i.e. that you are calling it on a clock which has no source clock. This made sense in the original design where the only way for a clock's frequency to change if it had a source clock was when that source clock changed. However, we subsequently added multiplier/divider support, but didn't look at what that meant for propagation. If a clock-management device changes the multiplier or divider value on a clock, it needs to propagate that change down to child clocks, even if the clock has a source clock set. So the assertion is now incorrect. Remove the assertion. Signed-off-by: Raphael Poggi <raphael.poggi@lynxleap.co.uk> Message-id: 20240419162951.23558-1-raphael.poggi@lynxleap.co.uk Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Rewrote the commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2024-04-30.gitlab-ci.d/cirrus: Remove the netbsd and openbsd jobsThomas Huth2-68/+0
During the past months, the netbsd and openbsd jobs in the Cirrus-CI were broken most of the time - the setup to run a BSD in KVM on Cirrus-CI from gitlab via the cirrus-run script was very fragile, and since the jobs were not run by default, it used to bitrot very fast. Now Cirrus-CI also introduce a limit on the amount of free CI minutes that you get there, so it is not appealing at all anymore to run these BSDs in this setup - it's better to run the checks locally via "make vm-build-openbsd" and "make vm-build-netbsd" instead. Thus let's remove these CI jobs now. Message-ID: <20240426113742.654748-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30.gitlab-ci.d/cirrus.yml: Shorten the runtime of the macOS and FreeBSD jobsThomas Huth1-0/+2
Cirrus-CI introduced limitations to the free CI minutes. To avoid that we are consuming them too fast, let's drop the usual targets that are not that important since they are either a subset of another target (like i386 or ppc being a subset of x86_64 or ppc64 respectively), or since there is still a similar target with the opposite endianness (like xtensa/xtensael, microblaze/microblazeel etc.). Message-ID: <20240429100113.53357-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30tests/qtest/ide-test: Verify READ NATIVE MAX ADDRESS is not limitedLev Kujawski1-1/+46
Verify that the ATA command READ NATIVE MAX ADDRESS returns the last valid CHS tuple for the native device rather than any limit established by INITIALIZE DEVICE PARAMETERS. Signed-off-by: Lev Kujawski <lkujaw@mailbox.org> Message-ID: <20221010085229.2431276-2-lkujaw@mailbox.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30hw/ide/core.c (cmd_read_native_max): Avoid limited device parametersLev Kujawski1-4/+17
Always use the native CHS device parameters for the ATA commands READ NATIVE MAX ADDRESS and READ NATIVE MAX ADDRESS EXT, not those limited by the ATA command INITIALIZE_DEVICE_PARAMETERS (introduced in patch 176e4961, hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command, 2022-07-07.) As stated by the ATA/ATAPI specification, "[t]he native maximum is the highest address accepted by the device in the factory default condition." Therefore this patch substitutes the native values in drive_heads and drive_sectors before calling ide_set_sector(). One consequence of the prior behavior was that setting zero sectors per track could lead to an FPE within ide_set_sector(). Thanks to Alexander Bulekov for reporting this issue. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1243 Signed-off-by: Lev Kujawski <lkujaw@mailbox.org> Message-ID: <20221010085229.2431276-1-lkujaw@mailbox.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30gitlab: remove stale s390x-all-linux-static conf hacksAlex Bennée1-3/+1
The libssh bug references 18.04 which we are no longer running. We don't need to disable glusterfs because a linux-user build shouldn't be trying to link to it anyway. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240426153938.1707723-4-alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30gitlab: migrate the s390x custom machine to 22.04Alex Bennée2-15/+15
20.04 is dead (from QEMU's point of view), long live 22.04! Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240426153938.1707723-3-alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30build-environment: make some packages optionalAlex Bennée1-3/+13
Upgrading the s390x runner exposed some packages are not available for it. Add an additional optional stage we only enable for arm64/x86_64 for now. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240426153938.1707723-2-alex.bennee@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30hw/char/stm32l4x5_usart: Fix memory corruption by adding correct class_sizeThomas Huth1-0/+1
"make check-qtest-aarch64" recently started failing on FreeBSD builds, and valgrind on Linux also detected that there is something fishy with the new stm32l4x5-usart: The code forgot to set the correct class_size here, so the various class_init functions in this file wrote beyond the allocated buffer when setting the subc->type field. Fixes: 4fb37aea7e ("hw/char: Implement STM32L4x5 USART skeleton") Message-ID: <20240429075908.36302-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30qga: Re-enable the qga-ssh-test when running without fuzzingThomas Huth1-3/+2
According to the comment in qga/meson.build, the test got disabled since there were problems with the fuzzing job. But instead of disabling this test completely, we should still be fine running it when fuzzing is disabled. Message-ID: <20240426162348.684143-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30stubs: Add missing qga stubsKonstantin Kostiuk1-1/+5
Compilation QGA without system and user fails ./configure --disable-system --disable-user --enable-guest-agent Link failure: /usr/bin/ld: libqemuutil.a.p/util_main-loop.c.o: in function `os_host_main_loop_wait': ../util/main-loop.c:303: undefined reference to `replay_mutex_unlock' /usr/bin/ld: ../util/main-loop.c:307: undefined reference to `replay_mutex_lock' /usr/bin/ld: libqemuutil.a.p/util_error-report.c.o: in function `error_printf': ../util/error-report.c:38: undefined reference to `error_vprintf' /usr/bin/ld: libqemuutil.a.p/util_error-report.c.o: in function `vreport': ../util/error-report.c:225: undefined reference to `error_vprintf' /usr/bin/ld: libqemuutil.a.p/util_qemu-timer.c.o: in function `timerlist_run_timers': ../util/qemu-timer.c:562: undefined reference to `replay_checkpoint' /usr/bin/ld: ../util/qemu-timer.c:530: undefined reference to `replay_checkpoint' /usr/bin/ld: ../util/qemu-timer.c:525: undefined reference to `replay_checkpoint' ninja: build stopped: subcommand failed. Fixes: 3a15604900 ("stubs: include stubs only if needed") Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com> Message-ID: <20240426121347.18843-2-kkostiuk@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30hw: misc: edu: use qemu_log_mask instead of hw_errorChris Friedt1-4/+8
Log a guest error instead of a hardware error when the guest tries to DMA to / from an invalid address. Signed-off-by: Chris Friedt <cfriedt@meta.com> Message-ID: <20221018122551.94567-3-cfriedt@meta.com> [thuth: Add missing #include statement, fix error reported by checkpatch.pl] Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30hw: misc: edu: rename local vars in edu_check_rangeChris Friedt1-8/+8
This serves to make the local variables a bit less ambiguous. The latter two arguments are named to match DMA_START, and DMA_SIZE. Signed-off-by: Chris Friedt <cfriedt@meta.com> Message-ID: <20221018122551.94567-2-cfriedt@meta.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30hw: misc: edu: fix 2 off-by-one errorsChris Friedt1-9/+8
In the case that size1 was zero, because of the explicit 'end1 > addr' check, the range check would fail and the error message would read as shown below. The correct comparison is 'end1 >= addr'. EDU: DMA range 0x40000-0x3ffff out of bounds (0x40000-0x40fff)! Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1254 Signed-off-by: Chris Friedt <cfriedt@meta.com> [thuth: Adjust patch with regards to the "end1 <= end2" check] Message-ID: <20221018122551.94567-1-cfriedt@meta.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_models_sysemu: Drop local @err in apply_cpu_model()Zhao Liu1-3/+1
Use @errp to fetch error information directly and drop the local variable @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-8-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_models: Make kvm_s390_apply_cpu_model() return booleanZhao Liu3-10/+10
As error.h suggested, the best practice for callee is to return something to indicate success / failure. So make kvm_s390_apply_cpu_model() return boolean and check the returned boolean in apply_cpu_model() instead of accessing @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-7-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_models: Drop local @err in get_max_cpu_model()Zhao Liu1-3/+1
Use @errp to fetch error information directly and drop the local variable @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-6-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_models: Make kvm_s390_get_host_cpu_model() return booleanZhao Liu3-12/+12
As error.h suggested, the best practice for callee is to return something to indicate success / failure. So make kvm_s390_get_host_cpu_model() return boolean and check the returned boolean in get_max_cpu_model() instead of accessing @err. Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-5-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_model: Drop local @err in s390_realize_cpu_model()Zhao Liu1-3/+1
Use @errp to fetch error information directly and drop the local variable @err. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-3-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-30target/s390x/cpu_model: Make check_compatibility() return booleanZhao Liu1-7/+7
As error.h suggested, the best practice for callee is to return something to indicate success / failure. With returned boolean, there's no need to check @err. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-ID: <20240425031232.1586401-2-zhao1.liu@intel.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2024-04-29Merge tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu into stagingRichard Henderson7-20/+26
trivial patches for 2024-04-29 # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEe3O61ovnosKJMUsicBtPaxppPlkFAmYvknIACgkQcBtPaxpp # Pln8ywf+LthaeFDBccSYDKE+bu0zGshog5wBvlD6PHH7+e/tL6y5rKBmoC8aa2Pv # 9Op57otEGAjOviLwFh+Xm78B6SwTweFwDlRsLDhzZUyVWMV6RqfPQ2Ix2rTGncCZ # t7hpHwnDqtHPkwqqEdXzNC6tlL5wjTlZLOK8osCpUz7Ji4Iqt79KaxGiuEjdHovb # DBTOzC1DbfmCEWf7UcoBFsoQLHhYwnasAC+obEGD2ahiIfetyqOwaS0QrpWiw/47 # fl4sfuFgI2n56AdEtD7PNDiHZaCJ7ZnvlAz4wXu4veqdefgKNi2vlBXKNc0DokNK # pHaBsEnFswjVsz5w2ynQRH+i3hMzWg== # =rRV+ # -----END PGP SIGNATURE----- # gpg: Signature made Mon 29 Apr 2024 05:28:34 AM PDT # gpg: using RSA key 7B73BAD68BE7A2C289314B22701B4F6B1A693E59 # gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>" [full] # gpg: aka "Michael Tokarev <mjt@debian.org>" [full] # gpg: aka "Michael Tokarev <mjt@corpit.ru>" [full] * tag 'pull-trivial-patches' of https://gitlab.com/mjt0k/qemu: checkpatch.pl: forbid strerrorname_np() target/riscv/kvm: remove sneaky strerrorname_np() instance target/loongarch/cpu.c: typo fix: expection backends/cryptodev-builtin: Fix local_error leaks scripts/checkpatch: Do not use mailmap scripts/checkpatch: Avoid author email mangled by qemu-*@nongnu.org target/ppc/cpu_init: Remove "PowerPC" prefix from the CPU list target/s390x/cpu_models: Rework the output of "-cpu help" target/i386/cpu: Remove "x86" prefix from the CPU list Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-29Merge tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu ↵Richard Henderson1-14/+48
into staging slirp: Use newer slirp_*_hostxfwd API Nicholas Ngai (1): net/slirp: Use newer slirp_*_hostxfwd API # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEqpLrvfAUiqYaQ7iu5IlMrEVBS7AFAmYu5OgACgkQ5IlMrEVB # S7DGOQ//cnW2fiXnj+ijmQ4+h8Yj2vCtGZ9+7D74Q6KSbY0AkYVhRm+qWJA1XJrR # Y7JvetqKGCxhol24x0aopDvcybIDU/EqFrxhmZY+dJhZWxfsvYpLGJ5TfulRA1gy # PSDYQi6LlwDJyQT08po2TLA0zSOmxycdrA8mTJuf8UHDiXnwcy9WjDFF1tCrGoN4 # LgvsUUpQ6y9fZQxbFyPFwtHkUeREvfhRPT0c5lNsF0Cot8uXt5YOyCc0XKjX1d0F # ucuCwv65gsIdcaDHcHIYhyKZX3lfAXAAaDe9njvISYcyOlyXOZS9df3tuMTeEW8S # wuN10WuQHI7mpLS/IomnmYxb16lyhhwLC9kmNVZt6jGfTYB/xHUeXb9gIsdkc05s # Cxy+VdxgnzGji6dOwufI8/ufWSti1PRB1yhZsmJtLC7MDOv5EJkxrmRXhWkr6LYZ # CU52uT7CsOTKdmmwdjTUqkfswB70Js68J33Rbm3VWJlnSBAQ/ioGt50r7tqFBwT8 # HQc4CqYBT58BPb7rKrUa6dCy1uAprYl2juU3vl/nHcp2zIxIar1yzQK3OG+3h6fZ # Mrg/C5l4WiEKFgdl5sMj1xJK15aC42/UyzxUFM12usKaOtKjQAIkjx6U7HCjwfdR # BZmxTx2u7jGm9a0R3qhVhZjmIIbfLoeEHepLMOAHN+TGAl0bcxc= # =22cZ # -----END PGP SIGNATURE----- # gpg: Signature made Sun 28 Apr 2024 05:08:08 PM PDT # gpg: using RSA key AA92EBBDF0148AA61A43B8AEE4894CAC45414BB0 # gpg: Good signature from "Samuel Thibault <samuel.thibault@ens-lyon.org>" [undefined] # gpg: aka "Samuel Thibault <sthibault@debian.org>" [undefined] # gpg: aka "Samuel Thibault <samuel.thibault@gnu.org>" [unknown] # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" [undefined] # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" [undefined] # gpg: aka "Samuel Thibault <samuel.thibault@aquilenet.fr>" [unknown] # gpg: aka "Samuel Thibault <samuel.thibault@u-bordeaux.fr>" [unknown] # gpg: aka "Samuel Thibault <sthibault@hypra.fr>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: AA92 EBBD F014 8AA6 1A43 B8AE E489 4CAC 4541 4BB0 * tag 'samuel-thibault' of https://people.debian.org/~sthibault/qemu: net/slirp: Use newer slirp_*_hostxfwd API Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-29checkpatch.pl: forbid strerrorname_np()Daniel Henrique Barboza1-0/+3
Commit d424db2354 removed an instance of strerrorname_np() because it was breaking building with musl libc. A recent RISC-V patch ended up re-introducing it again by accident. Put this function in the baddies list in checkpatch.pl to avoid this situation again. This is what it will look like next time: $ ./scripts/checkpatch.pl 0001-temp-test.patch ERROR: use strerror() instead of strerrorname_np() #22: FILE: target/riscv/kvm/kvm-cpu.c:1058: + strerrorname_np(errno)); total: 1 errors, 0 warnings, 10 lines checked Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-04-29target/riscv/kvm: remove sneaky strerrorname_np() instanceDaniel Henrique Barboza1-2/+2
Commit d424db2354 excluded some strerrorname_np() instances because they break musl libc builds. Another instance happened to slip by via commit d4ff3da8f4. Remove it before it causes trouble again. Fixes: d4ff3da8f4 (target/riscv/kvm: initialize 'vlenb' via get-reg-list) Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-04-29target/loongarch/cpu.c: typo fix: expectionMichael Tokarev1-1/+1
Fixes: 1590154ee437 ("target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'") Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2024-04-29backends/cryptodev-builtin: Fix local_error leaksLi Zhijian1-4/+5
It seems that this error does not need to be propagated to the upper, directly output the error to avoid the leaks Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283 Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode") Signed-off-by: Li Zhijian <lizhijian@fujitsu.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: zhenwei pi <pizhenwei@bytedance.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2024-04-29scripts/checkpatch: Do not use mailmapPhilippe Mathieu-Daudé1-3/+3
The .mailmap file fixes mistake we already did. Do not use it when running checkpatch.pl, otherwise we might commit the very same mistakes. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
generated by cgit v1.1 at 2025-07-10 03:09:47 +0000