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2019-03-06virtio-balloon: VIRTIO_BALLOON_F_FREE_PAGE_HINTWei Wang2-1/+290
The new feature enables the virtio-balloon device to receive hints of guest free pages from the free page vq. A notifier is registered to the migration precopy notifier chain. The notifier calls free_page_start after the migration thread syncs the dirty bitmap, so that the free page optimization starts to clear bits of free pages from the bitmap. It calls the free_page_stop before the migration thread syncs the bitmap, which is the end of the current round of ram save. The free_page_stop is also called to stop the optimization in the case when there is an error occurred in the process of ram saving. Note: balloon will report pages which were free at the time of this call. As the reporting happens asynchronously, dirty bit logging must be enabled before this free_page_start call is made. Guest reporting must be disabled before the migration dirty bitmap is synchronized. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Michael S. Tsirkin <mst@redhat.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-8-git-send-email-wei.w.wang@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Dropped kernel header update, fixed up CMD_ID_* name change
2019-03-06migration/ram.c: add the free page optimization enable flagWei Wang2-1/+18
This patch adds the free page optimization enable flag, and a function to set this flag. When the free page optimization is enabled, not all the pages are needed to be sent in the bulk stage. Why using a new flag, instead of directly disabling ram_bulk_stage when the optimization is running? Thanks for Peter Xu's reminder that disabling ram_bulk_stage will affect the use of compression. Please see save_page_use_compression. When xbzrle and compression are used, if free page optimizaion causes the ram_bulk_stage to be disabled, save_page_use_compression will return false, which disables the use of compression. That is, if free page optimization avoids the sending of half of the guest pages, the other half of pages loses the benefits of compression in the meantime. Using a new flag to let migration_bitmap_find_dirty skip the free pages in the bulk stage will avoid the above issue. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Michael S. Tsirkin <mst@redhat.com> CC: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-7-git-send-email-wei.w.wang@intel.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration/ram.c: add a notifier chain for precopyWei Wang4-3/+83
This patch adds a notifier chain for the memory precopy. This enables various precopy optimizations to be invoked at specific places. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Michael S. Tsirkin <mst@redhat.com> CC: Peter Xu <peterx@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-6-git-send-email-wei.w.wang@intel.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration: API to clear bits of guest free pages from the dirty bitmapWei Wang2-0/+49
This patch adds an API to clear bits corresponding to guest free pages from the dirty bitmap. Spilt the free page block if it crosses the QEMU RAMBlock boundary. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Michael S. Tsirkin <mst@redhat.com> CC: Peter Xu <peterx@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-5-git-send-email-wei.w.wang@intel.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration: use bitmap_mutex in migration_bitmap_clear_dirtyWei Wang1-1/+4
The bitmap mutex is used to synchronize threads to update the dirty bitmap and the migration_dirty_pages counter. For example, the free page optimization clears bits of free pages from the bitmap in an iothread context. This patch makes migration_bitmap_clear_dirty update the bitmap and counter under the mutex. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Michael S. Tsirkin <mst@redhat.com> CC: Peter Xu <peterx@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-4-git-send-email-wei.w.wang@intel.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06bitmap: bitmap_count_one_with_offsetWei Wang1-0/+13
Count the number of 1s in a bitmap starting from an offset. Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Juan Quintela <quintela@redhat.com> CC: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <1544516693-5395-3-git-send-email-wei.w.wang@intel.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06bitmap: fix bitmap_count_oneWei Wang1-0/+4
BITMAP_LAST_WORD_MASK(nbits) returns 0xffffffff when "nbits=0", which makes bitmap_count_one fail to handle the "nbits=0" case. It appears to be preferred to remain BITMAP_LAST_WORD_MASK identical to the kernel implementation that it is ported from. So this patch fixes bitmap_count_one to handle the nbits=0 case. Inital Discussion Link: https://www.mail-archive.com/qemu-devel@nongnu.org/msg554316.html Signed-off-by: Wei Wang <wei.w.wang@intel.com> CC: Juan Quintela <quintela@redhat.com> CC: Dr. David Alan Gilbert <dgilbert@redhat.com> CC: Peter Xu <peterx@redhat.com> Message-Id: <1544516693-5395-2-git-send-email-wei.w.wang@intel.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06tests: Add basic migration precopy tcp testJuan Quintela1-5/+105
Not sharing code from precopy/unix because we have to read back the tcp parameter. Signed-off-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20190227105128.1655-4-quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Fixup for clash with Yury's
2019-03-06migration: Create socket-address parameterJuan Quintela5-1/+77
It will be used to store the uri parameters. We want this only for tcp, so we don't set it for other uris. We need it to know what port is migration running. Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Removed DummyStruct as suggested by Eric & Markus --
2019-03-06tests: Add migration xbzrle testJuan Quintela1-0/+64
Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Juan Quintela <quintela@redhat.com> Message-Id: <20190227105128.1655-2-quintela@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Fixup for class with Yury's series
2019-03-06migration: Add capabilities validationYury Kotov1-0/+137
Currently we don't check which capabilities set in the source QEMU. We just expect that the target QEMU has the same enabled capabilities. Add explicit validation for capabilities to make sure that the target VM has them too. This is enabled for only new capabilities to keep compatibily. Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Message-Id: <20190215174548.2630-6-yury-kotov@yandex-team.ru> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Manual merge
2019-03-06tests/migration-test: Add a test for ignore-shared capabilityYury Kotov1-25/+109
Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Message-Id: <20190215174548.2630-5-yury-kotov@yandex-team.ru> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> dgilbert: Disabled the test for now, not happy on aarch64
2019-03-06migration: Add an ability to ignore shared RAM blocksYury Kotov6-54/+94
If ignore-shared capability is set then skip shared RAMBlocks during the RAM migration. Also, move qemu_ram_foreach_migratable_block (and rename) to the migration code, because it requires access to the migration capabilities. Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Message-Id: <20190215174548.2630-4-yury-kotov@yandex-team.ru> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration: Introduce ignore-shared capabilityYury Kotov3-1/+19
We want to use local migration to update QEMU for running guests. In this case we don't need to migrate shared (file backed) RAM. So, add a capability to ignore such blocks during live migration. Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Message-Id: <20190215174548.2630-3-yury-kotov@yandex-team.ru> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06exec: Change RAMBlockIterFunc definitionYury Kotov6-26/+65
Currently, qemu_ram_foreach_* calls RAMBlockIterFunc with many block-specific arguments. But often iter func needs RAMBlock*. This refactoring is needed for fast access to RAMBlock flags from qemu_ram_foreach_block's callback. The only way to achieve this now is to call qemu_ram_block_from_host (which also enumerates blocks). So, this patch reduces complexity of qemu_ram_foreach_block() -> cb() -> qemu_ram_block_from_host() from O(n^2) to O(n). Fix RAMBlockIterFunc definition and add some functions to read RAMBlock* fields witch were passed. Signed-off-by: Yury Kotov <yury-kotov@yandex-team.ru> Message-Id: <20190215174548.2630-2-yury-kotov@yandex-team.ru> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration/rdma: clang compilation fixMarcel Apfelbaum1-1/+4
Configuring QEMU with: ../configure --cc=clang --enable-rdma Leads to compilation error: CC migration/rdma.o CC migration/block.o qemu/migration/rdma.c:3615:58: error: taking address of packed member 'rkey' of class or structure 'RDMARegisterResult' may result in an unaligned pointer value [-Werror,-Waddress-of-packed-member] (uintptr_t)host_addr, NULL, &reg_result->rkey, ^~~~~~~~~~~~~~~~ Fix it by using a temp local variable. Signed-off-by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20190304184923.24215-1-marcel.apfelbaum@gmail.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-03-06migration: Cleanup during exitDr. David Alan Gilbert3-3/+16
Currently we cleanup the migration object as we exit main after the main_loop finishes; however if there's a migration running things get messy and we can end up with the migration thread still trying to access freed structures. We now take a ref to the object around the migration thread itself, so the act of dropping the ref during exit doesn't cause us to lose the state until the thread quits. Cancelling the migration during migration also tries to get the thread to quit. We do this a bit earlier; so hopefully migration gets out of the way before all the devices etc are freed. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190227164900.16378-1-dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2019-03-06migration/rdma: Fix qemu_rdma_cleanup null checkDr. David Alan Gilbert1-1/+3
If the migration fails before the channel is open (e.g. a bad address) we end up in the cleanup with rdma->channel==NULL. Spotted by Coverity: CID 1398634 Fixes: fbbaacab2758cb3f32a0 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190214185351.5927-1-dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-03-06migration: Fix cancel stateDr. David Alan Gilbert1-2/+9
During a cancelled migration there's a race where the fd can go into an error state before we get back around the migration loop and migration_detect_error transitions from cancelling->failed. Check for cancelled/cancelling and don't change the state. Red Hat bug: https://bugzilla.redhat.com/show_bug.cgi?id=1608649 Fixes: b23c2ade250 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20190219195928.12289-1-dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>
2019-03-05Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-mar-05-2019' ↵Peter Maydell71-213/+10376
into staging MIPS queue for March 5th, 2019 # gpg: Signature made Tue 05 Mar 2019 16:06:34 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-mar-05-2019: target/mips: Add tests for integer add MSA instruction group tests/tcg: target/mips: Add tests for MSA pack instructions tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructions tests/tcg: target/mips: Add tests for MIPS64R6 shift instructions tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructions tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructions tests/tcg: target/mips: Add tests for MIPS64R6 logic instructions tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructions tests/tcg: target/mips: Extend functionality of MSA wrapper macros tests/tcg: target/mips: Fix test utilities for 128-bit tests tests/tcg: target/mips: Add test utilities for 64-bit tests tests/tcg: target/mips: Add test utilities for 32-bit tests tests/tcg: target/mips: Add wrappers for various MSA instructions disas: nanoMIPS: Add graphical description of pool organization disas: nanoMIPS: Correct comments to handlers of some DSP instructions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-03-05' into ↵Peter Maydell20-292/+371
staging QAPI patches for 2019-03-05 # gpg: Signature made Tue 05 Mar 2019 16:47:17 GMT # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2019-03-05: qapi: Fix array first used in a different module tests/qapi-schema: Cover forward reference to sub-module tests: Rename UserDefNativeListUnion to UserDefListUnion qapi: Fix code generation for sub-modules in other directories qapi: Pass file name to QAPIGen constructor instead of methods tests/qapi-schema: Cover conditional arrays tests/qapi-schema: Make test-qapi.py print arrays Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05Merge remote-tracking branch ↵Peter Maydell29-270/+1028
'remotes/pmaydell/tags/pull-target-arm-20190305' into staging target-arm queue: * Fix PC test for LDM (exception return) * Implement ARMv8.0-SB * Implement ARMv8.0-PredInv * Implement ARMv8.4-CondM * Implement ARMv8.5-CondM * Implement ARMv8.5-FRINT * hw/arm/stellaris: Implement watchdog timer * virt: support more than 255GB of RAM # gpg: Signature made Tue 05 Mar 2019 16:49:47 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190305: (22 commits) hw/arm/stellaris: Implement watchdog timer hw/arm/virt: Bump the 255GB initial RAM limit hw/arm/virt: Check the VCPU PA range in TCG mode hw/arm/virt: Implement kvm_type function for 4.0 machine hw/arm/virt: Dynamic memory map depending on RAM requirements vl: Set machine ram_size, maxram_size and ram_slots earlier kvm: add kvm_arm_get_max_vm_ipa_size hw/boards: Add a MachineState parameter to kvm_type callback hw/arm/virt: Split the memory map description hw/arm/virt: Rename highmem IO regions hw/arm/boot: introduce fdt_add_memory_node helper target/arm: Implement ARMv8.5-FRINT target/arm: Restructure handle_fp_1src_{single, double} target/arm: Implement ARMv8.5-CondM target/arm: Implement ARMv8.4-CondM target/arm: Rearrange disas_data_proc_reg target/arm: Add set/clear_pstate_bits, share gen_ss_advance target/arm: Split helper_msr_i_pstate into 3 target/arm: Implement ARMv8.0-PredInv target/arm: Implement ARMv8.0-SB ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05target/mips: Add tests for integer add MSA instruction groupMateja Marjanovic26-0/+3926
These are the regression tests for integer addition MSA instruction - various flavors of instruction add (ADD, ADDS, HADD,...). Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1551718283-4487-3-git-send-email-mateja.marjanovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MSA pack instructionsAleksandar Markovic12-0/+1836
Add tests for MSA pack instructions. This includes following instructions: * PCKEV.B - pack even (bytes) * PCKEV.H - pack even (halfwords) * PCKEV.W - pack even (words) * PCKEV.D - pack even (doublewords) * PCKOD.B - pack odd (bytes) * PCKOD.H - pack odd (halfwords) * PCKOD.W - pack odd (words) * PCKOD.D - pack odd (doublewords) * VSHF.B - data preserving shuffle (bytes) * VSHF.H - data preserving shuffle (halfwords) * VSHF.W - data preserving shuffle (words) * VSHF.D - data preserving shuffle (doublewords) Each test consists of 80 test cases, so altogether there are 960 test cases. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-15-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MIPS64R6 int multiply instructionsAleksandar Markovic8-0/+1208
Add tests for MIPS64R6 integer multiply instructions: MUL, MUH, MULU, MUHU, DMUL, DMUH, DMULU, and DMUHU. MUH and MUHU require 64 bit inputs in the form of 64-bit sign-extended 32-bit inputs. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-14-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MIPS64R6 shift instructionsAleksandar Markovic6-0/+906
Add tests for MIPS64R6 shift instructions: SLLV, SRLV, SRAV, DSLLV, DSRLV, and DSRAV. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-13-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MIPS64R6 bit count instructionsAleksandar Markovic4-0/+576
Add tests for MIPS64R6 bit count instructions: CLO, CLZ, DCLO, and DCLZ. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-12-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MIPS64R6 bit swap instructionsAleksandar Markovic2-0/+288
Add tests for MIPS64R6 bit swap instructions: BITSWAP and DBITSWAP. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-11-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add tests for MIPS64R6 logic instructionsAleksandar Markovic4-0/+604
Add tests for MIPS64R6 logic instructions: AND, NOR, OR, and XOR. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-10-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add wrappers for some MIPS64R6 instructionsAleksandar Markovic1-0/+83
Add wrappers for some MIPS64R6 instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-9-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Extend functionality of MSA wrapper macrosAleksandar Markovic1-0/+51
Add macros that will allow testing cases when one of the source registers is identical to the destination register. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-8-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Fix test utilities for 128-bit testsAleksandar Markovic2-9/+10
Add "static" and "const" modifiers where appropriate, and fix other minor issues. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-7-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add test utilities for 64-bit testsAleksandar Markovic2-0/+286
Add test utilities for 64-bit tests. Some of MIPS64R6 instructions require 64-bit inputs to be 32-bit integers sign-extedned to 64 bits, hence the need for sets of such inputs. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-6-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add test utilities for 32-bit testsAleksandar Markovic2-0/+200
Add test utilities for 32-bit tests. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-5-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05tests/tcg: target/mips: Add wrappers for various MSA instructionsAleksandar Markovic1-0/+70
Add wrappers for various MSA integer instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-4-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05disas: nanoMIPS: Add graphical description of pool organizationAleksandar Markovic1-0/+102
Add graphical description of nanoMIPS instruction pool organization. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-3-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05disas: nanoMIPS: Correct comments to handlers of some DSP instructionsAleksandar Markovic1-204/+230
Correct comments to handlers of some DSP instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551800076-8104-2-git-send-email-aleksandar.markovic@rt-rk.com>
2019-03-05hw/arm/stellaris: Implement watchdog timerMichel Heily3-4/+100
Implement the watchdog timer for the stellaris boards. This device is a close variant of the CMSDK APB watchdog device, so we can model it by subclassing that device and tweaking the behaviour of some of its registers. Signed-off-by: Michel Heily <michelheily@gmail.com> Reviewed-by: Peter Maydell <petser.maydell@linaro.org> [PMM: rewrote commit message, fixed a few checkpatch nits, added comment giving the URL of the spec for the Stellaris variant of the watchdog device] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Bump the 255GB initial RAM limitEric Auger1-20/+1
Now we have the extended memory map (high IO regions beyond the scalable RAM) and dynamic IPA range support at KVM/ARM level we can bump the legacy 255GB initial RAM limit. The actual maximum RAM size now depends on the physical CPU and host kernel, in accelerated mode. In TCG mode, it depends on the VCPU AA64MMFR0.PARANGE. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-11-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Check the VCPU PA range in TCG modeEric Auger1-0/+17
We are about to allow the memory map to grow beyond 1TB and potentially overshoot the VCPU AA64MMFR0.PARANGE. In aarch64 mode and when highmem is set, let's check the VCPU PA range is sufficient to address the highest GPA of the memory map. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-10-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Implement kvm_type function for 4.0 machineEric Auger1-1/+38
This patch implements the machine class kvm_type() callback. It returns the number of bits requested to implement the whole GPA range including the RAM and IO regions located beyond. The returned value is passed though the KVM_CREATE_VM ioctl and this allows KVM to set the stage2 tables dynamically. To compute the highest GPA used in the memory map, kvm_type() must freeze the memory map by calling virt_set_memmap(). Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-9-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Dynamic memory map depending on RAM requirementsEric Auger2-6/+47
Up to now the memory map has been static and the high IO region base has always been 256GiB. This patch modifies the virt_set_memmap() function, which freezes the memory map, so that the high IO range base becomes floating, located after the initial RAM and the device memory. The function computes - the base of the device memory, - the size of the device memory, - the high IO region base - the highest GPA used in the memory map. Entries of the high IO region are assigned a base address. The device memory is initialized. The highest GPA used in the memory map will be used at VM creation to choose the requested IPA size. Setting all the existing highmem IO regions beyond the RAM allows to have a single contiguous RAM region (initial RAM and possible hotpluggable device memory). That way we do not need to do invasive changes in the EDK2 FW to support a dynamic RAM base. Still the user cannot request an initial RAM size greater than 255GB. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-8-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05vl: Set machine ram_size, maxram_size and ram_slots earlierEric Auger1-3/+3
The machine RAM attributes will need to be analyzed during the configure_accelerator() process. especially kvm_type() arm64 machine callback will use them to know how many IPA/GPA bits are needed to model the whole RAM range. So let's assign those machine state fields before calling configure_accelerator. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-7-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05kvm: add kvm_arm_get_max_vm_ipa_sizeEric Auger2-0/+23
Add the kvm_arm_get_max_vm_ipa_size() helper that returns the number of bits in the IPA address space supported by KVM. This capability needs to be known to create the VM with a specific IPA max size (kvm_type passed along KVM_CREATE_VM ioctl. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-6-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/boards: Add a MachineState parameter to kvm_type callbackEric Auger5-6/+8
On ARM, the kvm_type will be resolved by querying the KVMState. Let's add the MachineState handle to the callback so that we can retrieve the KVMState handle. in kvm_init, when the callback is called, the kvm_state variable is not yet set. Signed-off-by: Eric Auger <eric.auger@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-5-eric.auger@redhat.com [ppc parts] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Split the memory map descriptionEric Auger2-10/+53
In the prospect to introduce an extended memory map supporting more RAM, let's split the memory map array into two parts: - the former a15memmap, renamed base_memmap, contains regions below and including the RAM. MemMapEntries initialized in this array have a static size and base address. - extended_memmap, only initialized with entries located after the RAM. MemMapEntries initialized in this array only get their size initialized. Their base address is dynamically computed depending on the the top of the RAM, with same alignment as their size. Eventually base_memmap entries are copied into the extended_memmap array. Using two separate arrays however clarifies which entries are statically allocated and those which are dynamically allocated. This new split will allow to grow the RAM size without changing the description of the high IO entries. We introduce a new virt_set_memmap() helper function which "freezes" the memory map. We call it in machvirt_init as memory attributes of the machine are not yet set when virt_instance_init() gets called. The memory map is unchanged (the top of the initial RAM still is 256GiB). Then come the high IO regions with same layout as before. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-4-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/virt: Rename highmem IO regionsEric Auger3-23/+28
In preparation for a split of the memory map into a static part and a dynamic part floating after the RAM, let's rename the regions located after the RAM Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20190304101339.25970-3-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05hw/arm/boot: introduce fdt_add_memory_node helperShameer Kolothum1-20/+34
We introduce an helper to create a memory node. Signed-off-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190304101339.25970-2-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05target/arm: Implement ARMv8.5-FRINTRichard Henderson5-5/+173
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-03-05target/arm: Restructure handle_fp_1src_{single, double}Richard Henderson1-41/+49
This will allow sharing code that adjusts rmode beyond the existing users. Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190301200501.16533-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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