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2015-07-08virtio-pci: implement cfg capabilityMichael S. Tsirkin2-1/+78
spec says we must, so let's do it! Note: the implementation is incorrect for BE targets. Will fix with a patch on top, not a big deal now as the only user is seabios, used on x86 only. Tested-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08virtio: define virtio_pci_cfg_cap in header.Michael S. Tsirkin1-0/+6
Update virtio pci header from linux-next virtio maintainer tree. We already have VIRTIO_PCI_CAP_PCI_CFG, let's define the structure that goes with it. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08pcie: Set the "link active" in the link status registerBenjamin Herrenschmidt1-1/+1
Some firmwares can test that and assume the device hasn't come up if that bit isn't set Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08pci_regs.h: import from linuxMichael S. Tsirkin3-720/+721
It seems to make sense to import pci_regs.h from linux: why maintain our own? As a first step, move the header to standard-headers, and add it to the update script. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08virtio_net: reuse constants from linuxMichael S. Tsirkin2-12/+16
VIRTIO_NET_F_CTRL_GUEST_OFFLOADS now appears in the linux header, let's reuse it. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08hw/i386/pc: don't carry FDC from pc_basic_device_init() to pc_cmos_init()Laszlo Ersek4-11/+9
Thanks to the last patch, pc_cmos_init() doesn't need the (optional) board-default FDC any longer as an input parameter. Update pc_basic_device_init() not to hand it back to pc_init1() / pc_q35_init(), and update the latter not to carry the FDC to pc_cmos_init(). This simplifies the code. pc_init1() | pc_q35_init() pc_basic_device_init() pc_cmos_init() Cc: Jan Tomko <jtomko@redhat.com> Cc: John Snow <jsnow@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08hw/i386/pc: reflect any FDC @ ioport 0x3f0 in the CMOSLaszlo Ersek1-2/+55
With the pc-q35-2.4 machine type, if the user creates an ISA FDC manually: -device isa-fdc,driveA=drive-fdc0-0-0 \ -drive file=...,if=none,id=drive-fdc0-0-0,format=raw then the board-default FDC will be skipped, and only the explicitly requested FDC will exist. qtree-wise, this is correct; however such an FDC is currently not registered in the CMOS, because that code is only reached for the board-default FDC. The pc_cmos_init_late() one-shot reset handler -- one-shot because the CMOS is not reprogrammed during warm reset -- should search for any ISA FDC devices, created implicitly (by board code) or explicitly, and set the CMOS accordingly to the ISA FDC(s) with iobase=0x3f0: - if there is no such FDC, report both drives absent, - if there is exactly one such FDC, report its drives in the CMOS, - if there are more than one such FDCs, then pick one (it is not specified which one), and print a warning about the ambiguity. Cc: Jan Tomko <jtomko@redhat.com> Cc: John Snow <jsnow@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Reported-by: Jan Tomko <jtomko@redhat.com> Suggested-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08hw/i386/pc: factor out pc_cmos_init_floppy()Laszlo Ersek1-29/+38
Extract the pc_cmos_init_floppy() function from pc_cmos_init(). The function sets two RTC registers: floppy drive types (0x10), overwriting the earlier value in there), and REG_EQUIPMENT_BYTE (0x14), setting bits in the prior value. Cc: Jan Tomko <jtomko@redhat.com> Cc: John Snow <jsnow@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08ich9: implement strap SPKR pin logicPaulo Alcantara4-3/+28
If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode (ICH9 will disable the TCO Timer system reboot feature). The status of this strap is readable via the NO_REBOOT bit (CC: offset 0x3410:bit 5). The NO_REBOOT bit is set when SPKR pin on ICH9 is sampled high. This bit may be set or cleared by software if the strap is sampled low but may not override the strap when it indicates "No Reboot". This patch implements the logic where hardware has ability to set SPKR pin through a property named "noreboot" and it's sampled high by default. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-08tests: add testcase for TCO watchdog emulationPaulo Alcantara2-0/+462
This patch adds a testcase that covers the following: 1) TCO default values 2) first and second TCO timeout 3) watch and validate ticks counter through TCO_RLD register 4) maximum supported TCO timeout (0x3ff) 5) watchdog actions (pause/reset/shutdown/none) upon second TCO timeout 6) set and get of TCO control and status bits MST: The test does not pass yet, so it's disabled by default. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-07ich9: add TCO interface emulationPaulo Alcantara10-8/+439
This interface provides some registers within a 32-byte range and can be acessed through PCI-to-LPC bridge interface (PMBASE + 0x60). It's commonly used as a watchdog timer to detect system lockups through SMIs that are generated -- if TCO_EN bit is set -- on every timeout. If NO_REBOOT bit is not set in GCS (General Control and Status register), the system will be resetted upon second timeout if TCO_RLD register wasn't previously written to prevent timeout. This patch adds support to TCO watchdog logic and few other features like mapping NMIs to SMIs (NMI2SMI_EN bit), system intruder detection, etc. are not implemented yet. Signed-off-by: Paulo Alcantara <pcacjr@zytor.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-07acpi: split out ICH ACPI supportMichael S. Tsirkin3-1/+4
MIPS doesn't need it, and including it creates problem as we are adding dependency on ISA LPC bridge. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2015-07-07Revert "dataplane: allow virtio-1 devices"Cornelia Huck1-26/+21
This reverts commit f5a5628cf0b65b223fa0c9031714578dfac4cf04. This was an old patch that had been already superseded by b0e5d90eb ("dataplane: endianness-aware accesses"). Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
2015-07-07dataplane: fix cross-endian issuesGreg Kurz1-2/+4
Accesses to vring_avail_event and vring_used_event must honor the queue endianness. This patch allows cross-endian setups to use dataplane (tested with ppc64 on ppc64le, and vice-versa). Suggested-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-07-06Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream-smm' into ↵Peter Maydell22-344/+517
staging This series implements KVM support for SMM, and lets you enable/disable it through the "smm" property of x86 machine types. # gpg: Signature made Mon Jul 6 17:41:05 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream-smm: pc: add SMM property ich9: add smm_enabled field and arguments pc_piix: rename kvm_enabled to smm_enabled target-i386: register a separate KVM address space including SMRAM regions kvm-all: kvm_irqchip_create is not expected to fail kvm-all: add support for multiple address spaces kvm-all: make KVM's memory listener more generic kvm-all: move internal types to kvm_int.h kvm-all: remove useless typedef kvm-all: put kvm_mem_flags to more work target-i386: add support for SMBASE MSR and SMIs piix4/ich9: do not raise SMI on ACPI enable/disable commands linux-headers: Update to 4.2-rc1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06pc: add SMM propertyPaolo Bonzini7-2/+76
The property can take values on, off or auto. The default is "off" for KVM and pre-2.4 machines, otherwise "auto" (which makes it available on TCG or on new-enough kernels). Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06ich9: add smm_enabled field and argumentsPaolo Bonzini5-7/+11
Q35's ACPI device is hard-coding SMM availability to KVM. Place the logic where the board is created instead, so that it will be possible to override it. Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06pc_piix: rename kvm_enabled to smm_enabledPaolo Bonzini3-7/+7
We will enable SMM even if KVM is in use. Rename the field and arguments. Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06target-i386: register a separate KVM address space including SMRAM regionsPaolo Bonzini1-1/+40
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: kvm_irqchip_create is not expected to failPaolo Bonzini1-17/+18
KVM_CREATE_IRQCHIP should never fail, and so should its userspace wrapper kvm_irqchip_create. The function does not do anything if the irqchip capability is not available, as is the case for PPC. With this patch, kvm_arch_init can allocate memory and it will not be leaked. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: add support for multiple address spacesPaolo Bonzini2-7/+10
Make kvm_memory_listener_register public, and assign a kernel address space id to each KVMMemoryListener. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: make KVM's memory listener more genericPaolo Bonzini2-62/+94
No semantic change, but s->slots moves into a new struct KVMMemoryListener. KVM's memory listener becomes a member of struct KVMState, and becomes of type KVMMemoryListener. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: move internal types to kvm_int.hPaolo Bonzini2-17/+31
i386 code will have to define a different KVMMemoryListener. Create an internal header so that KVMSlot is not exposed outside. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: remove useless typedefPaolo Bonzini1-3/+1
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06kvm-all: put kvm_mem_flags to more workAndrew Jones1-22/+20
Currently kvm_mem_flags just translates bools to bits, let's make it also determine the bools first. This avoids its parameter list growing each time we add a flag. Signed-off-by: Andrew Jones <drjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06target-i386: add support for SMBASE MSR and SMIsPaolo Bonzini2-12/+94
Apart from the MSR, the smi field of struct kvm_vcpu_events has to be translated into the corresponding CPUX86State fields. Also, memory transaction flags depend on SMM state, so pull it from struct kvm_run on every exit from KVM to userspace. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06piix4/ich9: do not raise SMI on ACPI enable/disable commandsPaolo Bonzini2-0/+6
These commands are handled entirely by QEMU. Do not raise an SMI when they happen, because Windows (at least 2008r2) expects these commands to work and (depending on the value of APMC_EN at startup) the firmware might not have installed an SMI handler. When this happens (e.g. the kernel supports SMIs, or you are using TCG, but you have used "-machine smm=off") RIP is moved to 0x38000 where there is no code to execute. Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06linux-headers: Update to 4.2-rc1Alexey Kardashevskiy7-199/+121
This updates linux-headers against master 4.2-rc1 (commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754). This is the result of ./scripts/update-linux-headers.sh work. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell26-73/+299
* more of Peter Crosthwaite's multiarch preparation patches * unlocked MMIO support in KVM * support for compilation with ICC # gpg: Signature made Mon Jul 6 13:59:20 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: exec: skip MMIO regions correctly in cpu_physical_memory_write_rom_internal Stop including qemu-common.h in memory.h kvm: Switch to unlocked MMIO acpi: mark PMTIMER as unlocked kvm: Switch to unlocked PIO kvm: First step to push iothread lock out of inner run loop memory: let address_space_rw/ld*/st* run outside the BQL exec: pull qemu_flush_coalesced_mmio_buffer() into address_space_rw/ld*/st* memory: Add global-locking property to memory regions main-loop: introduce qemu_mutex_iothread_locked main-loop: use qemu_mutex_lock_iothread consistently Fix irq route entries exceeding KVM_MAX_IRQ_ROUTES cpu-defs: Move out TB_JMP defines include/exec: Move tb hash functions out include/exec: Move standard exceptions to cpu-all.h cpu-defs: Move CPU_TEMP_BUF_NLONGS to tcg memory_mapping: Rework cpu related includes cutils: allow compilation with icc qemu-common: add VEC_OR macro Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06exec: skip MMIO regions correctly in cpu_physical_memory_write_rom_internalPaolo Bonzini1-1/+13
Loading the BIOS in the mac99 machine is interesting, because there is a PROM in the middle of the BIOS region (from 16K to 32K). Before memory region accesses were clamped, when QEMU was asked to load a BIOS from 0xfff00000 to 0xffffffff it would put even those 16K from the BIOS file into the region. This is weird because those 16K were not actually visible between 0xfff04000 and 0xfff07fff. However, it worked. After clamping was added, this also worked. In this case, the cpu_physical_memory_write_rom_internal function split the write in three parts: the first 16K were copied, the PROM area (second 16K) were ignored, then the rest was copied. Problems then started with commit 965eb2f (exec: do not clamp accesses to MMIO regions, 2015-06-17). Clamping accesses is not done for MMIO regions because they can overlap wildly, and MMIO registers can be expected to perform full-width accesses based only on their address (with no respect for adjacent registers that could decode to completely different MemoryRegions). However, this lack of clamping also applied to the PROM area! cpu_physical_memory_write_rom_internal thus failed to copy the third range above, i.e. only copied the first 16K of the BIOS. In effect, address_space_translate is expecting _something else_ to do the clamping for MMIO regions if the incoming length is large. This "something else" is memory_access_size in the case of address_space_rw, so use the same logic in cpu_physical_memory_write_rom_internal. Reported-by: Alexander Graf <agraf@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Fixes: 965eb2f Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06Stop including qemu-common.h in memory.hPeter Maydell6-5/+22
Including qemu-common.h from other header files is generally a bad idea, because it means it's very easy to end up with a circular dependency. For instance, if we wanted to include memory.h from qom/cpu.h we'd end up with this loop: memory.h -> qemu-common.h -> cpu.h -> cpu-qom.h -> qom/cpu.h -> memory.h Remove the include from memory.h. This requires us to fix up a few other files which were inadvertently getting declarations indirectly through memory.h. The biggest change is splitting the fprintf_function typedef out into its own header so other headers can get at it without having to include qemu-common.h. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1435933104-15216-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2015-07-06Merge remote-tracking branch 'remotes/xtensa/tags/20150706-xtensa' into stagingPeter Maydell9-16/+70
Xtensa fixes: - add 64-bit floating point registers; - fix gdb register map construction. # gpg: Signature made Mon Jul 6 11:27:45 2015 BST using RSA key ID F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" * remotes/xtensa/tags/20150706-xtensa: target-xtensa: fix gdb register map construction target-xtensa: add 64-bit floating point registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06target-xtensa: fix gdb register map constructionMax Filippov7-7/+27
Due to different gdb overlay organization between windowed/call0 configurations core import script doesn't always work correctly. Simplify the script: always copy complete gdb register map from overlay, count registers at core registerstion time. Update existing cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-07-06target-xtensa: add 64-bit floating point registersMax Filippov4-9/+43
Xtensa ISA got specification for 64-bit floating point registers and opcodes, see ISA, 4.3.11 "Floating point coprocessor option". Add 64-bit FP registers. Although 64-bit floating point is currently not supported by xtensa translator, these registers need to be reported to gdb with proper size, otherwise it wouldn't find other registers. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2015-07-06Merge remote-tracking branch ↵Peter Maydell9-15/+63
'remotes/pmaydell/tags/pull-target-arm-20150706' into staging target-arm queue: * TLBI ALLEI1IS should operate on all CPUs, not just this one * Fix interval interrupt of cadence ttc in decrement mode * Implement YIELD insn to yield in ARM and Thumb translators * ARM GIC: reset all registers * arm_mptimer: fix timer shutdown and mode change * arm_mptimer: respect IT bit state # gpg: Signature made Mon Jul 6 10:58:27 2015 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20150706: arm_mptimer: Respect IT bit state arm_mptimer: Fix timer shutdown and mode change hw/intc/arm_gic_common.c: Reset all registers target-arm: Implement YIELD insn to yield in ARM and Thumb translators target-arm: Split DISAS_YIELD from DISAS_WFE Fix interval interrupt of cadence ttc when timer is in decrement mode target-arm: fix write helper for TLBI ALLE1IS Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06arm_mptimer: Respect IT bit stateDmitry Osipenko1-1/+1
The timer should fire the interrupt only if the IT (interrupt enable) bit state of the control register is enabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06arm_mptimer: Fix timer shutdown and mode changeDmitry Osipenko1-2/+9
The running timer can't be stopped because timer control code just doesn't handle disabling the timer. Fix it by deleting the timer if the enable bit is cleared. The timer won't start periodic ticking if a ONE-SHOT -> PERIODIC mode change happens after a one-shot tick was completed. Fix it by re-starting ticking if the timer isn't ticking right now. To avoid code churning, these two fixes are squashed in one commit. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06hw/intc/arm_gic_common.c: Reset all registersPeter Maydell1-3/+18
The arm_gic_common reset function was missing reset code for several of the GIC's state fields: * bpr[] * abpr[] * priority1[] * priority2[] * sgi_pending[] * irq_target[] (SMP configurations only) These probably went unnoticed because most guests will either never touch them, or will write to them in the process of configuring the GIC before enabling interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1435602345-32210-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-07-06target-arm: Implement YIELD insn to yield in ARM and Thumb translatorsPeter Maydell1-0/+7
Implement the YIELD instruction in the ARM and Thumb translators to actually yield control back to the top level loop rather than being a simple no-op. (We already do this for A64.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1435672316-3311-3-git-send-email-peter.maydell@linaro.org
2015-07-06target-arm: Split DISAS_YIELD from DISAS_WFEPeter Maydell4-3/+23
Currently we use DISAS_WFE for both WFE and YIELD instructions. This is functionally correct because at the moment both of them are implemented as "yield this CPU back to the top level loop so another CPU has a chance to run". However it's rather confusing that YIELD ends up calling HELPER(wfe), and if we ever want to implement real behaviour for WFE and SEV it's likely to trip us up. Split out the yield codepath to use DISAS_YIELD and a new HELPER(yield) function, and have HELPER(wfe) call HELPER(yield). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1435672316-3311-2-git-send-email-peter.maydell@linaro.org Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
2015-07-06Fix interval interrupt of cadence ttc when timer is in decrement modeJohannes Schlatow1-5/+4
The interval interrupt is not set if the timer is in decrement mode. This is because x >=0 and x < interval after leaving the while-loop. Signed-off-by: Johannes Schlatow <schlatow@ida.ing.tu-bs.de> Message-id: 20150630135821.51f3b4fd@johanness-latitude Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-06target-arm: fix write helper for TLBI ALLE1ISSergey Fedorov1-1/+1
TLBI ALLE1IS is an operation that does invalidate TLB entries on all PEs in the same Inner Sharable domain, not just on the current CPU. So we must use tlbiall_is_write() here. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1435676538-31345-1-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-05Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into stagingPeter Maydell9-268/+635
# gpg: Signature made Sat Jul 4 07:06:08 2015 BST using RSA key ID AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/ide-pull-request: (35 commits) ahci: fix sdb fis semantics qtest/ahci: halted ncq migration test ahci: Do not map cmd_fis to generate response ahci: ncq migration ahci: add get_cmd_header helper ahci: add cmd header to ncq transfer state qtest/ahci: halted NCQ test ahci: correct ncq sector count ahci: correct types in NCQTransferState ahci: add rwerror=stop support for ncq ahci: factor ncq_finish out of ncq_cb ahci: refactor process_ncq_command ahci: assert is_ncq for process_ncq ahci: stash ncq command ide: add limit to .prepare_buf() qtest/ahci: ncq migration test qtest/ahci: simple ncq data test libqos/ahci: Force all NCQ commands to be LBA48 libqos/ahci: set the NCQ tag on command_commit libqos/ahci: adjust expected NCQ interrupts ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-05Merge remote-tracking branch 'remotes/ehabkost/tags/numa-pull-request' into ↵Peter Maydell7-78/+219
staging NUMA queue, 2015-07-03 # gpg: Signature made Fri Jul 3 21:49:58 2015 BST using RSA key ID 984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/numa-pull-request: numa: API to lookup NUMA node by address numa: Store boot memory address range in node_info numa,pc-dimm: Store pc-dimm memory information in numa_info pc: Abort if HotplugHandlerClass::plug() fails pc,pc-dimm: Factor out reusable parts in pc_dimm_plug to a separate routine pc,pc-dimm: Extract hotplug related fields in PCMachineState to a structure Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-07-04ahci: fix sdb fis semanticsJohn Snow1-12/+17
There are two things to fix here: The first one is subtle: the PxSACT register in the AHCI HBA has different semantics from the field it is shadowing, the ACT field in the Set Device Bits FIS. In the HBA register, PxSACT acts as a bitfield indicating outstanding NCQ commands where a set bit indicates a pending NCQ operation. The FIS field however operates as an RWC register update to PxSACT, where a set bit indicates a *successfully* completed command. Correct the FIS semantics. At the same time, move the "clear finished" action to the SDB FIS generation instead of the register read to mimick how the other shadow registers work, which always just report the last reported value from a FIS, and not the most current values which may not have been reported by a FIS yet. Lastly and more simply, SATA 3.2 section 13.6.4.2 (and later sections) all specify that the Interrupt bit for the SDB FIS should always be set to one for NCQ commands. That's currently the only time we generate this FIS, so set it on all the time. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-16-git-send-email-jsnow@redhat.com
2015-07-04qtest/ahci: halted ncq migration testJohn Snow1-4/+15
Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-15-git-send-email-jsnow@redhat.com
2015-07-04ahci: Do not map cmd_fis to generate responseJohn Snow1-45/+5
The Register D2H FIS should copy the current values of the registers instead of just parroting back the same values the guest sent back to it. In this case, the SECTOR COUNT variables are actually not generally meaningful in terms of standard commands (See ATA8-AC3 Section 9.2 Normal Outputs), so it actually probably doesn't matter what we put in here. Meanwhile, we do need to use the Register update FIS from the NCQ pathways (in error cases), so getting rid of references to cur_cmd here is a win for AHCI concurrency. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-14-git-send-email-jsnow@redhat.com
2015-07-04ahci: ncq migrationJohn Snow1-1/+50
Migrate the NCQ queue. This is solely for the benefit of halted commands, since anything else should have completed and had any relevant status flushed to the HBA registers already. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-13-git-send-email-jsnow@redhat.com
2015-07-04ahci: add get_cmd_header helperJohn Snow1-3/+12
cur_cmd is an internal bookmark that points to the current AHCI Command Header being processed by the AHCI state machine. With NCQ needing to occasionally rely on some of the same AHCI helpers, we cannot use cur_cmd and will need to grab explicit pointers instead. In an attempt to begin relying on the cur_cmd pointer less, add a helper to let us specifically get the pointer to the command header of particular interest. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-12-git-send-email-jsnow@redhat.com
2015-07-04ahci: add cmd header to ncq transfer stateJohn Snow2-5/+7
While the rest of the AHCI device can rely on a single bookmarked pointer for the AHCI Command Header currently being processed, NCQ is asynchronous and may have many commands in flight simultaneously. Add a cmdh pointer to the ncq_tfs object and make the sglist prepare function take an AHCICmdHeader pointer so we can be explicit about where we'd like to build SGlists from. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1435767578-32743-11-git-send-email-jsnow@redhat.com
generated by cgit v1.1 at 2024-12-24 00:22:38 +0000