index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
Files
Lines
2023-01-06
hw/intc/loongarch_pch_msi: add irq number property
Tianrui Zhao
4
-10
/
+36
2023-01-06
hw/intc: sifive_plic: Fix the pending register range check
Bin Meng
1
-2
/
+3
2023-01-06
hw/riscv: opentitan: Drop "hartid-base" and "priority-base" initialization
Bin Meng
1
-2
/
+0
2023-01-06
hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0
Bin Meng
6
-7
/
+8
2023-01-06
hw/riscv: virt: Fix the value of "riscv, ndev" in the dtb
Bin Meng
2
-4
/
+4
2023-01-06
hw/riscv: sifive_u: Avoid using magic number for "riscv, ndev"
Bin Meng
1
-1
/
+2
2023-01-06
hw/riscv: sifive_e: Fix the number of interrupt sources of PLIC
Bin Meng
1
-1
/
+6
2023-01-06
hw/riscv: microchip_pfsoc: Fix the number of interrupt sources of PLIC
Bin Meng
1
-1
/
+1
2023-01-06
hw/intc: sifive_plic: Update "num-sources" property default value
Bin Meng
1
-1
/
+7
2023-01-06
hw/intc: sifive_plic: Use error_setg() to propagate the error up via errp in ...
Bin Meng
1
-3
/
+4
2023-01-06
hw/intc: sifive_plic: Improve robustness of the PLIC config parser
Bin Meng
1
-8
/
+16
2023-01-06
hw/intc: sifive_plic: Drop PLICMode_H
Bin Meng
2
-2
/
+0
2023-01-06
hw/riscv: spike: Remove misleading comments
Bin Meng
1
-1
/
+0
2023-01-06
hw/riscv: Sort machines Kconfig options in alphabetical order
Bin Meng
1
-7
/
+9
2023-01-06
hw/riscv: Fix opentitan dependency to SIFIVE_PLIC
Bin Meng
1
-0
/
+1
2023-01-06
hw/intc: Select MSI_NONBROKEN in RISC-V AIA interrupt controllers
Bin Meng
1
-0
/
+2
2023-01-06
hw/riscv: Select MSI_NONBROKEN in SIFIVE_PLIC
Bin Meng
2
-5
/
+1
2023-01-06
RISC-V: Add Zawrs ISA extension support
Christoph Muellner
5
-0
/
+64
2023-01-06
target/riscv: Clear mstatus.MPRV when leaving M-mode for priv spec 1.12+
Bin Meng
1
-0
/
+6
2023-01-06
target/riscv: Simplify helper_sret() a little bit
Bin Meng
1
-14
/
+6
2023-01-06
target/riscv: Set pc_succ_insn for !rvc illegal insn
Richard Henderson
4
-8
/
+44
2023-01-06
target/riscv: Fix mret exception cause when no pmp rule is configured
Bin Meng
1
-1
/
+1
2023-01-06
hw/intc: sifive_plic: fix out-of-bound access of source_priority array
Jim Shu
1
-1
/
+11
2023-01-06
hw/{misc, riscv}: pfsoc: add system controller as unimplemented
Conor Dooley
6
-6
/
+95
2023-01-06
hw/riscv: pfsoc: add missing FICs as unimplemented
Conor Dooley
2
-52
/
+65
2023-01-06
hw/misc: pfsoc: add fabric clocks to ioscb
Conor Dooley
2
-0
/
+7
2023-01-06
target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state()
Bin Meng
1
-0
/
+4
2023-01-06
target/riscv: support cache-related PMU events in virtual mode
Jim Shu
1
-1
/
+1
2023-01-06
hw/riscv: virt: Remove the redundant ipi-id property
Atish Patra
2
-5
/
+0
2023-01-06
target/riscv: Typo fix in sstc() predicate
Anup Patel
1
-1
/
+1
2023-01-06
hw/intc: sifive_plic: Renumber the S irqs for numa support
Frédéric Pétrot
1
-2
/
+2
2023-01-06
target/riscv: Add itrigger_enabled field to CPURISCVState
LIU Zhiwei
4
-2
/
+20
2023-01-06
target/riscv: Enable native debug itrigger
LIU Zhiwei
1
-0
/
+72
2023-01-06
target/riscv: Add itrigger support when icount is enabled
LIU Zhiwei
4
-0
/
+65
2023-01-06
target/riscv: Add itrigger support when icount is not enabled
LIU Zhiwei
9
-11
/
+131
2023-01-06
target/riscv: generate virtual instruction exception
Mayuresh Chitale
1
-1
/
+7
2023-01-06
target/riscv: smstateen check for h/s/envcfg
Mayuresh Chitale
1
-7
/
+80
2023-01-06
target/riscv: Add smstateen support
Mayuresh Chitale
4
-0
/
+378
2023-01-06
hw/riscv/opentitan: add aon_timer base unimpl
Wilfred Mallawa
2
-0
/
+4
2023-01-06
hw/riscv/opentitan: bump opentitan
Wilfred Mallawa
2
-13
/
+17
2023-01-06
tcg/riscv: Fix base register for user-only qemu_ld/st
Richard Henderson
1
-17
/
+22
2023-01-06
tcg/riscv: Fix reg overlap case in tcg_out_addsub2
Richard Henderson
1
-2
/
+8
2023-01-06
tcg/riscv: Fix range matched by TCG_CT_CONST_M12
Richard Henderson
1
-3
/
+16
2023-01-06
target/riscv: Fix PMP propagation for tlb
LIU Zhiwei
3
-70
/
+42
2023-01-06
i386: SGX: remove deprecated member of SGXInfo
Paolo Bonzini
4
-32
/
+21
2023-01-06
target/i386: Add SGX aex-notify and EDECCSSA support
Kai Huang
1
-2
/
+2
2023-01-06
util: remove support -chardev tty and -chardev parport
Paolo Bonzini
5
-49
/
+10
2023-01-06
util: remove support for hex numbers with a scaling suffix
Paolo Bonzini
4
-19
/
+19
2023-01-06
KVM: remove support for kernel-irqchip=off
Paolo Bonzini
6
-15
/
+25
2023-01-06
docs: do not talk about past removal as happening in the future
Paolo Bonzini
1
-3
/
+2
[prev]
[next]