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| author | Bin Meng <bmeng@tinylab.org> | 2022-12-05 14:53:03 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | 4c48aad122b9dd4d96184828d7172cc62dae01c5 (patch) | |
| tree | 212161ecc4fff5e54baf6564ad5552e51d921c19 | |
| parent | bb22d391121fc0de42a04d1ed99f602441ea70e1 (diff) | |
| download | qemu-4c48aad122b9dd4d96184828d7172cc62dae01c5.zip qemu-4c48aad122b9dd4d96184828d7172cc62dae01c5.tar.gz qemu-4c48aad122b9dd4d96184828d7172cc62dae01c5.tar.bz2 | |
target/riscv: Fix mret exception cause when no pmp rule is configured
The priv spec v1.12 says:
If no PMP entry matches an M-mode access, the access succeeds. If
no PMP entry matches an S-mode or U-mode access, but at least one
PMP entry is implemented, the access fails. Failed accesses generate
an instruction, load, or store access-fault exception.
At present the exception cause is set to 'illegal instruction' but
should have been 'instruction access fault'.
Fixes: d102f19a2085 ("target/riscv/pmp: Raise exception if no PMP entry is configured")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221205065303.204095-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/op_helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 09f1f51..d7af7f0 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -202,7 +202,7 @@ target_ulong helper_mret(CPURISCVState *env) if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_get_num_rules(env) && (prev_priv != PRV_M)) { - riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + riscv_raise_exception(env, RISCV_EXCP_INST_ACCESS_FAULT, GETPC()); } target_ulong prev_virt = get_field(env->mstatus, MSTATUS_MPV); |