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2023-11-07virtio-gpu: replace PIXMAN for region/rect testMarc-André Lureau2-19/+70
Use a simpler implementation for rectangle geometry & intersect, drop the need for (more complex) PIXMAN functions. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
2023-11-07qmp/hmp: disable screendump if PIXMAN is missingMarc-André Lureau4-1/+8
The command requires color conversion and line-by-line feeding. We could have a simple fallback for simple formats though. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07ui/vc: console-vc requires PIXMANMarc-André Lureau3-1/+37
Add stubs for the fallback paths. get_vc() now returns NULL by default if !PIXMAN. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07ui/console: allow to override the default VCMarc-André Lureau3-10/+33
If a display is backed by a specialized VC, allow to override the default "vc:80Cx24C". As suggested by Paolo, if the display doesn't implement a VC (get_vc() returns NULL), use a fallback that will use a muxed console on stdio. This changes the behaviour of "qemu -display none", to create a muxed serial/monitor by default (on TTY & not daemonized). Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07vl: move display early init before default devicesMarc-André Lureau1-13/+18
The next commit needs to have the display registered itself before creating the default VCs. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07vl: simplify display_remote logicMarc-André Lureau1-5/+1
Bump the display_remote variable when the -vnc option is parsed, just like -spice. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07qemu-options: define -vnc only #ifdef CONFIG_VNCMarc-André Lureau3-16/+11
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07vl: drop needless -spice checksMarc-André Lureau1-6/+1
Since commit 5324e3e958e ("qemu-options: define -spice only #ifdef CONFIG_SPICE"), it is unnecessary to check at runtime for "-spice" option. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07ui: add pixman-minimal.hMarc-André Lureau2-0/+197
This is a tiny subset of PIXMAN API that is used pervasively in QEMU codebase to manage images and identify the underlying format. It doesn't seems worth to wrap this in a QEMU-specific API. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com>
2023-11-07ui: compile out some qemu-pixman functions when !PIXMANMarc-André Lureau2-2/+11
Those functions require the PIXMAN library. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07build-sys: drop needless warning pragmas for old pixmanMarc-André Lureau1-4/+0
Since commit 236f282c1c7 ("configure: check for pixman-1 version"), QEMU requires >= 0.21.8. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-11-07build-sys: add a "pixman" featureMarc-André Lureau5-2/+18
For now, pixman is mandatory, but we set config_host.h and Kconfig. Once compilation is fixed, "pixman" will become actually optional. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2023-11-07Merge tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi22-1443/+2577
target/hppa: Implement PA2.0 instructions hw/hppa: Map astro chip 64-bit I/O mem hw/hppa: Turn on 64-bit cpu for C3700 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJqDEdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV8n5Qf/R15CvXGMgjDJjoV2 # ILMFM+Rpg17SR2yu060sEZ01R3iHdobeCcDB184K0RI9JLrpcBFar+PeF023o9fn # O9MnfIyL6/ggzaeIpQ9AD2uT0HJMU9hLFoyQqQvnhDHHcT34raL2+Zkrkb2vvauH # XET7awXN9xYCnY4ALrfcapzlrHqI77ahz0vReUWPxk7eGY2ez8dEOiFW2WLBmuMx # mAFAMrFQhq66GjoMDl8JiGHD/KBJQ9X4eUAEotS27lTCOYU0ryA6dWBGqBSTWCUa # smpxkeGQKOew+717HV1H4FdCRYG1Rgm7yFN423JULeew+T7DHvfe0K55vMIulx5I # g3oVZA== # =dxC7 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 11:00:01 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-pa-20231106' of https://gitlab.com/rth7680/qemu: (85 commits) hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU only hw/hppa: Turn on 64-bit CPU for C3700 machine hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memory hw/pci-host/astro: Map Astro chip into 64-bit I/O memory region target/hppa: Improve interrupt logging target/hppa: Update IIAOQ, IIASQ for pa2.0 target/hppa: Create raise_exception_with_ior target/hppa: Add unwind_breg to CPUHPPAState target/hppa: Clear upper bits in mtctl for pa1.x target/hppa: Avoid async_safe_run_on_cpu on uniprocessor system target/hppa: Add pa2.0 cpu local tlb flushes target/hppa: Implement pa2.0 data prefetch instructions linux-user/hppa: Drop EXCP_DUMP from handled exceptions hw/hppa: Translate phys addresses for the cpu include/hw/elf: Remove truncating signed casts target/hppa: Return zero for r0 from load_gpr target/hppa: Precompute zero into DisasContext target/hppa: Fix interruption based on default PSW target/hppa: Implement PERMH target/hppa: Implement MIXH, MIXW ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07Merge tag 'pull-riscv-to-apply-20231107' of ↵Stefan Hajnoczi29-258/+1326
https://github.com/alistair23/qemu into staging Third RISC-V PR for 8.2 * Rename ext_icboz to ext_zicboz * Rename ext_icbom to ext_zicbom * Rename ext_icsr to ext_zicsr * Rename ext_ifencei to ext_zifencei * Add RISC-V Virtual IRQs and IRQ filtering support * Change default linux-user cpu to 'max' * Update 'virt' machine core limit * Add query-cpu-model-expansion API * Rename epmp to smepmp and expose the extension * Clear pmp/smepmp bits on reset * Ignore pmp writes when RW=01 * Support zicntr/zihpm flags and disable support * Correct CSR_MSECCFG operations * Update mail address for Weiwei Li * Update RISC-V vector crypto to ratified v1.0.0 * Clear the Ibex/OpenTitan SPI interrupts even if disabled * Set the OpenTitan priv to 1.12.0 * Support discontinuous PMU counters # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmVJoOEACgkQr3yVEwxT # gBPwcw/5AXgSVu521IHpobofq4Skc2rpO9P0Hep3IniBuS+5+h2XM3fwWNBaeeGj # LZgdXDrCfcCnPuFh2I5j1D885xJDncDF4LET9EFtxK+BTT8eC5JpaCnORdV3Zd2T # C7qdq1r4J/wKBel3cAz1jlLXc2Pssle4NFaMZGmOGlNX/mLJUYkI6BwKG9wNiCI+ # cCRQW5bEv9g8XzPYPsIKhX9aTegDKdV5x4Xj3YyVs8qkZTVM7Ona8GTpy6eShNfL # h/RW+yvSxLwfKC9YJHesjI1oqhLsAuA7hFu5AVHiedFNAD5FevMZsZwrqjrmeBOG # 5awBw9XgfXFFl7jQ0VQVRknt/PFANzTmGGbjLUkaXgJ6iTmH7oIMzwbkx2pM/0Qd # HV2EboUPe5rJl0SNhcDMCJkYJYpt4z6TVXFpN5p10WU4K1AJXZf9P3YkChcxWiSK # B4DlY4ax3W77voySwbKCvJRIRWCFQZmtl7doFY5dEQz2ERcNfI7VIB1GKIj7BlGm # AVTCc5G9KghsaB8q0BzYbDplzCggdaaUBRgpIgLS/n22GKJlOisFwMCawWquPkEw # i0t3ftt+Ket4Qnnq+dO4W3ehR4qW1/XatCWgQ3NCSgUeS4/9VK3h/nz5t+L7iKwp # mjp86gNN11wcJRsBIIV7nOAmSAs9ybCm2F4J6YAyh3n1IlRVN0Q= # =2A+W # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 10:28:49 HKT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20231107' of https://github.com/alistair23/qemu: (49 commits) docs/about/deprecated: Document RISC-V "pmu-num" deprecation target/riscv: Add "pmu-mask" property to replace "pmu-num" target/riscv: Use existing PMU counter mask in FDT generation target/riscv: Don't assume PMU counters are continuous target/riscv: Propagate error from PMU setup target/riscv: cpu: Set the OpenTitan priv to 1.12.0 hw/ssi: ibex_spi_host: Clear the interrupt even if disabled disas/riscv: Replace TABs with space disas/riscv: Add support for vector crypto extensions disas/riscv: Add rv_codec_vror_vi for vror.vi disas/riscv: Add rv_fmt_vd_vs2_uimm format target/riscv: Move vector crypto extensions to riscv_cpu_extensions target/riscv: Expose Zvks[c|g] extnesion properties target/riscv: Add cfg properties for Zvks[c|g] extensions target/riscv: Expose Zvkn[c|g] extnesion properties target/riscv: Add cfg properties for Zvkn[c|g] extensions target/riscv: Expose Zvkb extension property target/riscv: Replace Zvbb checking by Zvkb target/riscv: Add cfg property for Zvkb extension target/riscv: Expose Zvkt extension property ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-07Merge tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi36-1304/+1529
util: Add cpuinfo for loongarch64 tcg/loongarch64: Use cpuinfo.h tcg/loongarch64: Improve register allocation for INDEX_op_qemu_ld_a*_i128 host/include/loongarch64: Add atomic16 load and store tcg: Move expanders out of line tcg/mips: Always implement movcond tcg/mips: Implement neg opcodes tcg/loongarch64: Implement neg opcodes tcg: Make movcond and neg required opcodes tcg: Optimize env memory operations tcg: Canonicalize sub of immediate to add tcg/sparc64: Implement tcg_out_extrl_i64_i32 # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmVJpT0dHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9i7QgAtjxUB3y/caCPp0Me # 3cXYtpL1vNxx+cTESGMlmIRSji+cEOxYSpnY0itxXcKpcwP8Au8eoTe85NxyIllg # 2R/SA2jlmrmiipI+bwb0UBCy+BzUfMgmegA88K2W22J0fetwIy19PN9ORmYdLiYE # /pWNFOSPzhYEJgOw7V2MwciUv3llolMOfxU7VT4oVaCknZRsyaGUwl4uTT4GdPuK # p29O9nziyKDmNTqJ9SKKll5bzwCMAgkn2lUcMGf+rpl7ZxjgvysUYrGXKmOnj4Uu # eCU2d3ZHoSspcYEjbFASlyPd7z5apGI8Iq2K35FUhURFPv06Su/bIGOOD4ujP2Qp # vc/bFQ== # =Mvaf # -----END PGP SIGNATURE----- # gpg: Signature made Tue 07 Nov 2023 10:47:25 HKT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20231106' of https://gitlab.com/rth7680/qemu: (35 commits) tcg/sparc64: Implement tcg_out_extrl_i64_i32 tcg/optimize: Canonicalize sub2 with constants to add2 tcg/optimize: Canonicalize subi to addi during optimization tcg: Canonicalize subi to addi during opcode generation tcg/optimize: Split out arg_new_constant tcg: Eliminate duplicate env store operations tcg/optimize: Optimize env memory operations tcg/optimize: Split out cmp_better_copy tcg/optimize: Pipe OptContext into reset_ts tcg: Don't free vector results tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} tcg/loongarch64: Implement neg opcodes tcg/mips: Implement neg opcodes tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} tcg/mips: Always implement movcond tcg/mips: Split out tcg_out_setcond_int tcg: Move tcg_temp_free_* out of line tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line tcg: Move tcg_constant_* out of line tcg: Unexport tcg_gen_op*_{i32,i64} ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-06hw/hppa: Allow C3700 with 64-bit and B160L with 32-bit CPU onlyHelge Deller1-0/+24
Prevent that users try to boot a 64-bit only C3700 machine with a 32-bit CPU, and to boot a 32-bit only B160L machine with a 64-bit CPU. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06hw/hppa: Turn on 64-bit CPU for C3700 machineHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06hw/pci-host/astro: Trigger CPU irq on CPU HPA in high memoryHelge Deller1-1/+1
The CPU HPA is in the high F-region on PA2.0 CPUs, so use F_EXTEND() to trigger interrupt request at the right CPU HPA address. Note that the cpu_hpa value comes out of the IRT, which doesn't store the higher addresss bits. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06hw/pci-host/astro: Map Astro chip into 64-bit I/O memory regionHelge Deller1-3/+6
Map Astro into high F-region and add alias for 32-bit OS in low region. Signed-off-by: Helge Deller <deller@gmx.de>
2023-11-06target/hppa: Improve interrupt loggingRichard Henderson1-8/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update IIAOQ, IIASQ for pa2.0Richard Henderson2-18/+38
These registers have a different format for pa2.0. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Create raise_exception_with_iorRichard Henderson1-13/+51
Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add unwind_breg to CPUHPPAStateRichard Henderson3-2/+20
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Clear upper bits in mtctl for pa1.xHelge Deller1-1/+7
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson1-1/+7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller5-12/+84
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson1-1/+9
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06linux-user/hppa: Drop EXCP_DUMP from handled exceptionsRichard Henderson1-4/+0
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06hw/hppa: Translate phys addresses for the cpuRichard Henderson1-46/+71
Hack the machine to use pa2.0 physical layout when required, using the PSW.W=0 absolute to physical mapping. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06include/hw/elf: Remove truncating signed castsRichard Henderson1-7/+10
There's nothing about elf that specifically requires signed vs unsigned. This is very much a target-specific preference. In the meantime, casting low and high from uint64_t back to Elf_SWord to uint64_t discards high bits that might have been set by translate_fn. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson1-3/+1
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson1-16/+18
Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix interruption based on default PSWHelge Deller2-4/+16
The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement PERMHRichard Henderson2-0/+31
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson2-0/+60
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson4-2/+76
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson2-0/+40
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HAVGRichard Henderson4-0/+22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson4-0/+53
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson4-1/+79
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson1-4/+4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson1-80/+82
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson1-37/+58
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson1-33/+13
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson1-505/+407
Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson11-299/+135
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06hw/hppa: Use uint32_t instead of target_uregRichard Henderson1-6/+6
The size of target_ureg is going to change. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson4-13/+100
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement STDBYRichard Henderson4-5/+213
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson2-0/+8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-14 19:22:10 +0000