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2021-05-02target/mips: Move tlb_helper.c to tcg/sysemu/Philippe Mathieu-Daudé5-9/+6
Move tlb_helper.c to the tcg/sysemu/ subdir, along with the following 3 declarations to tcg-internal.h: - cpu_mips_tlb_flush() - cpu_mips_translate_address() - r4k_invalidate_tlb() Simplify tlb_helper.c #ifdef'ry because files in tcg/sysemu/ are only build when sysemu mode is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-22-f4bug@amsat.org>
2021-05-02target/mips: Restrict mmu_init() to TCGPhilippe Mathieu-Daudé3-4/+3
mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-21-f4bug@amsat.org>
2021-05-02target/mips: Move sysemu TCG-specific code to tcg/sysemu/ subfolderPhilippe Mathieu-Daudé7-167/+179
Move cp0_helper.c and mips-semi.c to the new tcg/sysemu/ folder, adapting the Meson machinery. Move the opcode definitions to tcg/sysemu_helper.h.inc. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-20-f4bug@amsat.org>
2021-05-02target/mips: Restrict cpu_mips_get_random() / update_pagemask() to TCGPhilippe Mathieu-Daudé2-4/+9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-19-f4bug@amsat.org>
2021-05-02target/mips: Move physical addressing code to sysemu/physaddr.cPhilippe Mathieu-Daudé4-255/+282
Declare get_physical_address() with local scope and move it along with mips_cpu_get_phys_page_debug() to sysemu/physaddr.c new file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-18-f4bug@amsat.org>
2021-05-02target/mips: Move sysemu specific files under sysemu/ subfolderPhilippe Mathieu-Daudé6-7/+13
Move sysemu-specific files under the new sysemu/ subfolder and adapt the Meson machinery. Update the KVM MIPS entry in MAINTAINERS. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-17-f4bug@amsat.org>
2021-05-02target/mips: Move cpu_signal_handler definition aroundPhilippe Mathieu-Daudé1-5/+4
We have 2 blocks guarded with #ifdef for sysemu, which are simply separated by the cpu_signal_handler definition. To simplify the following commits which involve various changes in internal.h, first join the sysemu-guarded blocks. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-16-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_tlb_fill()Philippe Mathieu-Daudé2-10/+36
tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-15-f4bug@amsat.org>
2021-05-02target/mips: Add simple user-mode mips_cpu_do_interrupt()Philippe Mathieu-Daudé5-5/+39
The #ifdef'ry hides that the user-mode implementation of mips_cpu_do_interrupt() simply sets exception_index = EXCP_NONE. Add this simple implementation to tcg/user/tlb_helper.c, and the corresponding Meson machinery to build this file when user emulation is configured. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-14-f4bug@amsat.org>
2021-05-02target/mips: Introduce tcg-internal.h for TCG specific declarationsPhilippe Mathieu-Daudé2-4/+23
We will gradually move TCG-specific declarations to a new local header: "tcg-internal.h". To keep review simple, first add this header with 2 TCG prototypes, which we are going to move in the next 2 commits. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-13-f4bug@amsat.org>
2021-05-02meson: Introduce meson_user_arch source set for arch-specific user-modePhilippe Mathieu-Daudé1-0/+6
Similarly to the 'target_softmmu_arch' source set which allows to restrict target-specific sources to system emulation, add the equivalent 'target_user_arch' set for user emulation. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-12-f4bug@amsat.org>
2021-05-02target/mips: Extract load/store helpers to ldst_helper.cPhilippe Mathieu-Daudé3-259/+289
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-11-f4bug@amsat.org>
2021-05-02target/mips: Merge do_translate_address into cpu_mips_translate_addressPhilippe Mathieu-Daudé3-24/+9
Currently cpu_mips_translate_address() calls raise_mmu_exception(), and do_translate_address() calls cpu_loop_exit_restore(). This API split is dangerous, we could call cpu_mips_translate_address without returning to the main loop. As there is only one caller, it is trivial (and safer) to merge do_translate_address() back to cpu_mips_translate_address(). Reported-by: Richard Henderson <richard.henderson@linaro.org> Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-10-f4bug@amsat.org>
2021-05-02target/mips: Declare mips_env_set_pc() inlined in "internal.h"Philippe Mathieu-Daudé3-20/+14
Rename set_pc() as mips_env_set_pc(), declare it inlined and use it in cpu.c and op_helper.c. Reported-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210428170410.479308-9-f4bug@amsat.org>
2021-05-02target/mips: Turn printfpr() macro into a proper functionPhilippe Mathieu-Daudé1-27/+23
Turn printfpr() macro into a proper function: fpu_dump_fpr(). Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-8-f4bug@amsat.org>
2021-05-02target/mips: Restrict mips_cpu_dump_state() to cpu.cPhilippe Mathieu-Daudé3-78/+77
As mips_cpu_dump_state() is only used once to initialize the CPUClass::dump_state handler, we can move it to cpu.c to keep it symbol local. Beside, this handler is used by all accelerators, while the translate.c file targets TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-7-f4bug@amsat.org>
2021-05-02target/mips: Optimize CPU/FPU regnames[] arraysPhilippe Mathieu-Daudé3-4/+4
Since all entries are no more than 4 bytes (including nul terminator), can save space and pie runtime relocations by declaring regnames[] as array of 4 const char. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-6-f4bug@amsat.org>
2021-05-02target/mips: Make CPU/FPU regnames[] arrays globalPhilippe Mathieu-Daudé4-14/+17
The CPU/FPU regnames[] arrays is used in mips_tcg_init() and mips_cpu_dump_state(), which while being in translate.c is not specific to TCG. To be able to move mips_cpu_dump_state() to cpu.c, which is compiled for all accelerator, we need to make the regnames[] arrays global to target/mips/ by declaring them in "internal.h". Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-5-f4bug@amsat.org>
2021-05-02target/mips: Move msa_reset() to new source filePhilippe Mathieu-Daudé3-36/+61
mips_cpu_reset() is used by all accelerators, and calls msa_reset(), which is defined in msa_helper.c. Beside msa_reset(), the rest of msa_helper.c is only useful to the TCG accelerator. To be able to restrict this helper file to TCG, we need to move msa_reset() out of it. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-4-f4bug@amsat.org>
2021-05-02target/mips: Move IEEE rounding mode array to new source filePhilippe Mathieu-Daudé3-8/+19
restore_msa_fp_status() is declared inlined in fpu_helper.h, and uses the ieee_rm[] array. Therefore any code calling restore_msa_fp_status() must have access to this ieee_rm[] array. kvm_mips_get_fpu_registers(), which is in target/mips/kvm.c, calls restore_msa_fp_status. Except this tiny array, the rest of fpu_helper.c is only useful for the TCG accelerator. To be able to restrict fpu_helper.c to TCG, we need to move the ieee_rm[] array to a new source file. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-3-f4bug@amsat.org>
2021-05-02target/mips: Simplify meson TCG rulesPhilippe Mathieu-Daudé1-3/+2
We already have the mips_tcg_ss source set for TCG-specific files, use it for mxu_translate.c and tx79_translate.c to simplify a bit. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-2-f4bug@amsat.org>
2021-05-02target/mips: Make check_cp0_enabled() return a booleanPhilippe Mathieu-Daudé2-2/+9
To avoid callers to emit dead code if check_cp0_enabled() raise an exception, let it return a boolean value, whether CP0 is enabled or not. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210420193453.1913810-4-f4bug@amsat.org>
2021-05-02target/mips: Migrate missing CPU fieldsPhilippe Mathieu-Daudé1-6/+15
Add various missing fields to the CPU migration vmstate: - CP0_VPControl & CP0_GlobalNumber (01bc435b44b 2016-02-03) - CMGCRBase (c870e3f52ca 2016-03-15) - CP0_ErrCtl (0d74a222c27 2016-03-25) - MXU GPR[] & CR (eb5559f67dc 2018-10-18) - R5900 128-bit upper half (a168a796e1c 2019-01-17) This is a migration break. Fixes: 01bc435b44b ("target-mips: implement R6 multi-threading") Fixes: c870e3f52ca ("target-mips: add CMGCRBase register") Fixes: 0d74a222c27 ("target-mips: make ITC Configuration Tags accessible to the CPU") Fixes: eb5559f67dc ("target/mips: Introduce MXU registers") Fixes: a168a796e1c ("target/mips: Introduce 32 R5900 multimedia registers") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210423220044.3004195-1-f4bug@amsat.org>
2021-05-02target/mips: Remove spurious LOG_UNIMP of MTHC0 opcodePhilippe Mathieu-Daudé1-0/+1
When running with '-d unimp' all MTHC0 opcode executed are logged as unimplemented... Add the proper 'return' statement missed from commit 5204ea79ea7. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210422081055.2349216-1-f4bug@amsat.org>
2021-05-02target/mips: Add missing CP0 check to nanoMIPS RDPGPR / WRPGPR opcodesPhilippe Mathieu-Daudé1-0/+2
Per the nanoMIPS32 Instruction Set Technical Reference Manual, Revision 01.01, Chapter 3. "Instruction Definitions": The Read/Write Previous GPR opcodes "require CP0 privilege". Add the missing CP0 checks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210421185007.2231855-1-f4bug@amsat.org>
2021-05-02target/mips: Fix CACHEE opcode (CACHE using EVA addressing)Philippe Mathieu-Daudé1-1/+3
The CACHEE opcode "requires CP0 privilege". The pseudocode checks in the ISA manual is: if is_eva and not C0.Config5.EVA: raise exception('RI') if not IsCoprocessor0Enabled(): raise coprocessor_exception(0) Add the missing checks. Inspired-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210420175426.1875746-1-f4bug@amsat.org>
2021-05-02hw/isa/piix4: Use qdev_get_gpio_in_named() to get ISA IRQPhilippe Mathieu-Daudé1-2/+3
Since commit 078778c5a55 ("piix4: Add an i8259 Interrupt Controller") the TYPE_PIIX4_PCI_DEVICE exposes the ISA input IRQs as "isa" alias. Use this alias to get IRQ for the power management PCI function. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210324182902.692419-1-f4bug@amsat.org>
2021-05-02Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210501' ↵Peter Maydell7-85/+112
into staging Include cleanups. Decodetree enhancements for power10. # gpg: Signature made Sat 01 May 2021 19:50:22 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210501: decodetree: Extend argument set syntax to allow types decodetree: Add support for 64-bit instructions decodetree: More use of f-strings decodetree: Introduce whex and whexC helpers exec: Remove accel/tcg/ from include paths Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-01decodetree: Extend argument set syntax to allow typesRichard Henderson3-21/+36
Rather than force all structure members to be 'int', allow the type of the member to be specified. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: Add support for 64-bit instructionsLuis Fernando Fujita Pires1-7/+14
Allow '64' to be specified for the instruction width command line params and use the appropriate extract and deposit functions in that case. This will be used to implement the new 64-bit Power ISA 3.1 instructions. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Luis Pires <luis.pires@eldorado.org.br> Message-Id: <CP2PR80MB3668E123E2EFDB0ACD3A46F1DA759@CP2PR80MB3668.lamprd80.prod.outlook.com> [rth: Drop the change to the field type; use bitop_width instead of separate variables for extract/deposit; use "ull" for 64-bit constants.] Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: More use of f-stringsRichard Henderson1-27/+23
Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01decodetree: Introduce whex and whexC helpersRichard Henderson1-28/+38
Form a hex constant of the appropriate insnwidth. Begin using f-strings on changed lines. Reviewed-by: Luis Pires <luis.pires@eldorado.org.br> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-01exec: Remove accel/tcg/ from include pathsPhilippe Mathieu-Daudé4-7/+6
When TCG is enabled, the accel/tcg/ include path is added to the project global include search list. This accel/tcg/ directory contains a header named "internal.h" which, while intented to be internal to accel/tcg/, is accessible by all files compiled when TCG is enabled. This might lead to problem with other directories using the same "internal.h" header name: $ git ls-files | fgrep /internal.h accel/tcg/internal.h include/hw/ide/internal.h target/hexagon/internal.h target/mips/internal.h target/ppc/internal.h target/s390x/internal.h As we don't need to expose accel/tcg/ internals to the rest of the code base, simplify by removing it from the include search list, and include the accel/tcg/ public headers relative to the project root search path (which is already in the generic include search path). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210413081008.3409459-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-04-30Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-04-30' into ↵Peter Maydell14-111/+429
staging QAPI patches patches for 2021-04-30 # gpg: Signature made Fri 30 Apr 2021 12:42:32 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2021-04-30: (25 commits) qapi/error.py: enable mypy checks qapi/error: Add type hints qapi/error.py: enable pylint checks qapi/error.py: move QAPIParseError to parser.py qapi/error: assert QAPISourceInfo is not None qapi/error: Make QAPISourceError 'col' parameter optional qapi/error: Use Python3-style super() qapi/error: Repurpose QAPIError as an abstract base exception class qapi/expr: Update authorship and copyright information qapi/expr.py: Use tuples instead of lists for static data qapi/expr.py: Add docstrings qapi/expr: Only explicitly prohibit 'Kind' nor 'List' for type names qapi/expr.py: enable pylint checks qapi/expr.py: Remove single-letter variable qapi/expr.py: Consolidate check_if_str calls in check_if qapi/expr.py: add type hint annotations qapi/expr.py: Modify check_keys to accept any Collection qapi/expr.py: Add casts in a few select cases qapi/expr.py: Check type of union and alternate 'data' member qapi/expr.py: move string check upwards in check_type ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into stagingPeter Maydell22-679/+1279
Block layer patches - Fix permission update order problems with block graph changes - qemu-img convert: Unshare write permission for source - vhost-user-blk: Fail gracefully on too large queue size # gpg: Signature made Fri 30 Apr 2021 11:27:51 BST # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kevin/tags/for-upstream: (39 commits) vhost-user-blk: Fail gracefully on too large queue size qemu-img convert: Unshare write permission for source block: Add BDRV_O_NO_SHARE for blk_new_open() block: refactor bdrv_node_check_perm() block: rename bdrv_replace_child_safe() to bdrv_replace_child() block: refactor bdrv_child_set_perm_safe() transaction action block: inline bdrv_replace_child() block: inline bdrv_check_perm_common() block: drop unused permission update functions block: bdrv_reopen_multiple: refresh permissions on updated graph block: bdrv_reopen_multiple(): move bdrv_flush to separate pre-prepare block: add bdrv_set_backing_noperm() transaction action block: make bdrv_refresh_limits() to be a transaction action block: make bdrv_unset_inherits_from to be a transaction action block: drop ignore_children for permission update functions block/backup-top: drop .active block: introduce bdrv_drop_filter() block: add bdrv_remove_filter_or_cow transaction action block: adapt bdrv_append() for inserting filters block: split out bdrv_replace_node_noperm() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-04-30qapi/error.py: enable mypy checksJohn Snow1-5/+0
Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-9-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error: Add type hintsJohn Snow1-2/+9
No functional change. Note: QAPISourceError's info parameter is Optional[] because schema.py treats the info property of its various classes as Optional to accommodate built-in types, which have no source. See prior commit 'qapi/error: assert QAPISourceInfo is not None'. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-8-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error.py: enable pylint checksJohn Snow1-2/+1
Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-7-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error.py: move QAPIParseError to parser.pyJohn Snow2-15/+21
Keeping it in error.py will create some cyclic import problems when we add types to the QAPISchemaParser. Callers don't need to know the details of QAPIParseError unless they are parsing or dealing directly with the parser, so this won't create any harsh new requirements for callers in the general case. Update error.py with a little docstring that gives a nod to where the error may now be found. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-6-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error: assert QAPISourceInfo is not NoneJohn Snow1-0/+1
Built-in stuff is not parsed from a source file, and therefore have no QAPISourceInfo. If such None info was used for reporting an error, built-in stuff would be broken. Programming error. Instead of reporting a confusing error with bogus source location then, we better crash. We currently crash only if self.col was set. Assert that self.info is not None in order to crash reliably. We can not yet change the type of the initializer to prove this cannot happen at static analysis time before the remainder of the code is fully typed. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-5-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error: Make QAPISourceError 'col' parameter optionalJohn Snow2-7/+4
It's already treated as optional, with one direct caller and some subclass callers passing 'None'. Make it officially optional, which requires moving the position of the argument to come after all required parameters. QAPISemError becomes functionally identical to QAPISourceError. Keep the name to preserve its semantic meaning and avoid code churn, but remove the now-useless __init__ wrapper. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-4-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error: Use Python3-style super()John Snow1-1/+1
Missed in commit 2cae67bcb5 "qapi: Use super() now we have Python 3". Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210421192233.3542904-3-jsnow@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/error: Repurpose QAPIError as an abstract base exception classJohn Snow3-5/+14
Rename QAPIError to QAPISourceError, and then create a new QAPIError class that serves as the basis for all of our other custom exceptions, without specifying any class properties. This leaves QAPIError as a package-wide error class that's suitable for any current or future errors. (Right now, we don't have any errors that DON'T also want to specify a Source location, but this MAY change. In these cases, a common abstract ancestor would be desired.) Add docstrings to explain the intended function of each error class. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421192233.3542904-2-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr: Update authorship and copyright informationJohn Snow1-1/+2
Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421182032.3521476-18-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr.py: Use tuples instead of lists for static dataJohn Snow1-2/+2
It is -- maybe -- possibly -- three nanoseconds faster. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20210421182032.3521476-17-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr.py: Add docstringsJohn Snow1-5/+251
Now with more :words:! Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421182032.3521476-16-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr: Only explicitly prohibit 'Kind' nor 'List' for type namesJohn Snow1-3/+3
Per list review: qapi-code-gen.txt reserves suffixes Kind and List only for type names, but the code rejects them for events and commands, too. It turns out we reject them earlier anyway: In check_name_upper() for event names, and in check_name_lower() for command names. Still, adjust the code for clarity over what precisely we are guarding against. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421182032.3521476-15-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr.py: enable pylint checksJohn Snow1-1/+0
Signed-off-by: John Snow <jsnow@redhat.com> Tested-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Tested-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20210421182032.3521476-14-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr.py: Remove single-letter variableJohn Snow1-7/+7
Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421182032.3521476-13-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-04-30qapi/expr.py: Consolidate check_if_str calls in check_ifJohn Snow1-17/+16
This is a small rewrite to address some minor style nits. Don't compare against the empty list to check for the empty condition, and move the normalization forward to unify the check on the now-normalized structure. With the check unified, the local nested function isn't needed anymore and can be brought down into the normal flow of the function. With the nesting level changed, shuffle the error strings around a bit to get them to fit in 79 columns. Note: although ifcond is typed as Sequence[str] elsewhere, we *know* that the parser will produce real, bona-fide lists. It's okay to check isinstance(ifcond, list) here. Signed-off-by: John Snow <jsnow@redhat.com> Message-Id: <20210421182032.3521476-12-jsnow@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
generated by cgit v1.1 at 2024-08-22 14:31:38 +0000