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2022-01-21
target/riscv: Adjust csr write mask with XLEN
LIU Zhiwei
2
-5
/
+10
2022-01-21
target/riscv: Relax debug check for pm write
LIU Zhiwei
1
-0
/
+3
2022-01-21
target/riscv: Use gdb xml according to max mxlen
LIU Zhiwei
2
-24
/
+55
2022-01-21
target/riscv: Extend pc for runtime pc write
LIU Zhiwei
1
-3
/
+19
2022-01-21
target/riscv: Ignore the pc bits above XLEN
LIU Zhiwei
1
-1
/
+1
2022-01-21
target/riscv: Create xl field in env
LIU Zhiwei
5
-32
/
+46
2022-01-21
target/riscv: Sign extend pc for different XLEN
LIU Zhiwei
4
-9
/
+27
2022-01-21
target/riscv: Sign extend link reg for jal and jalr
LIU Zhiwei
2
-6
/
+2
2022-01-21
target/riscv: Don't save pc when exception return
LIU Zhiwei
3
-9
/
+6
2022-01-21
target/riscv: Adjust pmpcfg access with mxl
LIU Zhiwei
2
-8
/
+23
2022-01-21
roms/opensbi: Remove ELF images
Anup Patel
5
-6
/
+0
2022-01-21
hw/riscv: Remove macros for ELF BIOS image names
Anup Patel
2
-4
/
+2
2022-01-21
hw/riscv: spike: Allow using binary firmware as bios
Anup Patel
4
-28
/
+52
2022-01-21
target/riscv: rvv-1.0: Allow Zve32f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns
Frank Chang
1
-0
/
+3
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns
Frank Chang
1
-0
/
+18
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns
Frank Chang
1
-0
/
+21
2022-01-21
target/riscv: rvv-1.0: Add Zve32f support for configuration insns
Frank Chang
1
-2
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve32f extension into RISC-V
Frank Chang
5
-4
/
+7
2022-01-21
target/riscv: rvv-1.0: Allow Zve64f extension to be turned on
Frank Chang
1
-0
/
+1
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns
Frank Chang
1
-3
/
+6
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns
Frank Chang
1
-7
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns
Frank Chang
1
-1
/
+2
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns
Frank Chang
1
-10
/
+31
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns
Frank Chang
1
-2
/
+25
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns
Frank Chang
1
-6
/
+33
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for load and store insns
Frank Chang
1
-4
/
+15
2022-01-21
target/riscv: rvv-1.0: Add Zve64f support for configuration insns
Frank Chang
1
-2
/
+4
2022-01-21
target/riscv: rvv-1.0: Add Zve64f extension into RISC-V
Frank Chang
5
-2
/
+16
2022-01-21
softmmu/device_tree: Remove redundant pointer assignment
Yanan Wang
1
-5
/
+4
2022-01-21
softmmu/device_tree: Silence compiler warning with --enable-sanitizers
Thomas Huth
1
-2
/
+2
2022-01-21
target/riscv: enable riscv kvm accel
Yifei Jiang
1
-0
/
+2
2022-01-21
target/riscv: Support virtual time context synchronization
Yifei Jiang
1
-0
/
+30
2022-01-21
target/riscv: Implement virtual time adjusting with vm state changing
Yifei Jiang
1
-0
/
+15
2022-01-21
target/riscv: Add kvm_riscv_get/put_regs_timer
Yifei Jiang
2
-0
/
+79
2022-01-21
target/riscv: Add host cpu type
Yifei Jiang
2
-0
/
+16
2022-01-21
target/riscv: Handle KVM_EXIT_RISCV_SBI exit
Yifei Jiang
2
-1
/
+113
2022-01-21
target/riscv: Support setting external interrupt by KVM
Yifei Jiang
4
-1
/
+28
2022-01-21
target/riscv: Support start kernel directly by KVM
Yifei Jiang
10
-32
/
+164
2022-01-21
target/riscv: Implement kvm_arch_put_registers
Yifei Jiang
1
-1
/
+103
2022-01-21
target/riscv: Implement kvm_arch_get_registers
Yifei Jiang
1
-1
/
+111
2022-01-21
target/riscv: Implement function kvm_arch_init_vcpu
Yifei Jiang
1
-1
/
+33
2022-01-21
target/riscv: Add target/riscv/kvm.c to place the public kvm interface
Yifei Jiang
2
-0
/
+134
2022-01-21
update-linux-headers: Add asm-riscv/kvm.h
Yifei Jiang
1
-0
/
+128
2022-01-21
hw: timer: ibex_timer: update/add reg address
Wilfred Mallawa
1
-1
/
+10
2022-01-21
riscv: opentitan: fixup plic stride len
Wilfred Mallawa
1
-1
/
+1
2022-01-21
hw: timer: ibex_timer: Fixup reading w/o register
Wilfred Mallawa
2
-10
/
+5
2022-01-20
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20220120-...
Peter Maydell
31
-763
/
+1457
2022-01-20
hw/intc/arm_gicv3: Check for !MEMTX_OK instead of MEMTX_ERROR
Philippe Mathieu-Daudé
1
-2
/
+2
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