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| author | LIU Zhiwei <zhiwei_liu@c-sky.com> | 2022-01-20 20:20:37 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:57 +1000 |
| commit | 83b519b8a44d6b7d9b9d9763e7189061e116215d (patch) | |
| tree | a28937805f66159e8e2eb1b10e95e81d437d3367 | |
| parent | 47bdec821b8dda7658e3e802a26b9bd8319cdb49 (diff) | |
| download | qemu-83b519b8a44d6b7d9b9d9763e7189061e116215d.zip qemu-83b519b8a44d6b7d9b9d9763e7189061e116215d.tar.gz qemu-83b519b8a44d6b7d9b9d9763e7189061e116215d.tar.bz2 | |
target/riscv: Adjust csr write mask with XLEN
Write mask is representing the bits we care about.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-11-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/insn_trans/trans_rvi.c.inc | 12 | ||||
| -rw-r--r-- | target/riscv/op_helper.c | 3 |
2 files changed, 10 insertions, 5 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 04d3ea2..631bc1f 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -924,7 +924,8 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc, static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) { - if (get_xl(ctx) < MXL_RV128) { + RISCVMXL xl = get_xl(ctx); + if (xl < MXL_RV128) { TCGv src = get_gpr(ctx, a->rs1, EXT_NONE); /* @@ -935,7 +936,8 @@ static bool trans_csrrw(DisasContext *ctx, arg_csrrw *a) return do_csrw(ctx, a->csr, src); } - TCGv mask = tcg_constant_tl(-1); + TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX : + (target_ulong)-1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } else { TCGv srcl = get_gpr(ctx, a->rs1, EXT_NONE); @@ -1013,7 +1015,8 @@ static bool trans_csrrc(DisasContext *ctx, arg_csrrc *a) static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) { - if (get_xl(ctx) < MXL_RV128) { + RISCVMXL xl = get_xl(ctx); + if (xl < MXL_RV128) { TCGv src = tcg_constant_tl(a->rs1); /* @@ -1024,7 +1027,8 @@ static bool trans_csrrwi(DisasContext *ctx, arg_csrrwi *a) return do_csrw(ctx, a->csr, src); } - TCGv mask = tcg_constant_tl(-1); + TCGv mask = tcg_constant_tl(xl == MXL_RV32 ? UINT32_MAX : + (target_ulong)-1); return do_csrrw(ctx, a->rd, a->csr, src, mask); } else { TCGv src = tcg_constant_tl(a->rs1); diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 67693cb..1a75ba1 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -50,7 +50,8 @@ target_ulong helper_csrr(CPURISCVState *env, int csr) void helper_csrw(CPURISCVState *env, int csr, target_ulong src) { - RISCVException ret = riscv_csrrw(env, csr, NULL, src, -1); + target_ulong mask = env->xl == MXL_RV32 ? UINT32_MAX : (target_ulong)-1; + RISCVException ret = riscv_csrrw(env, csr, NULL, src, mask); if (ret != RISCV_EXCP_NONE) { riscv_raise_exception(env, ret, GETPC()); |