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2019-06-13target/arm: Convert VFP VLDR and VSTR to decodetreePeter Maydell3-20/+82
Convert the VFP single load/store insns VLDR and VSTR to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VFP two-register transfer insns to decodetreePeter Maydell3-44/+77
Convert the VFP two-register transfer instructions to decodetree (in the v8 Arm ARM these are the "Advanced SIMD and floating-point 64-bit move" encoding group). Again, we expand out the sequences involving gen_vfp_msr() and gen_msr_vfp(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert "single-precision" register moves to decodetreePeter Maydell3-145/+168
Convert the "single-precision" register moves to decodetree: * VMSR * VMRS * VMOV between general purpose register and single precision Note that the VMSR/VMRS conversions make our handling of the "should this UNDEF?" checks consistent between the two instructions: * VMSR to MVFR0, MVFR1, MVFR2 now UNDEF from EL0 (previously was a nop) * VMSR to FPSID now UNDEFs from EL0 or if VFPv3 or better (previously was a nop) * VMSR to FPINST and FPINST2 now UNDEF if VFPv3 or better (previously would write to the register, which had no guest-visible effect because we always UNDEF reads) We also tighten up the decode: we were previously underdecoding some SBZ or SBO bits. The conversion of VMOV_single includes the expansion out of the gen_mov_F0_vreg()/gen_vfp_mrs() and gen_mov_vreg_F0()/gen_vfp_msr() sequences into the simpler direct load/store of the TCG temp via neon_{load,store}_reg32(): we know in the new function that we're always single-precision, we don't need to use the old-and-deprecated cpu_F0* TCG globals, and we don't happen to have the declaration of gen_vfp_msr() and gen_vfp_mrs() at the point in the file where the new function is. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert "double-precision" register moves to decodetreePeter Maydell3-81/+185
Convert the "double-precision" register moves to decodetree: this covers VMOV scalar-to-gpreg, VMOV gpreg-to-scalar and VDUP. Note that the conversion process has tightened up a few of the UNDEF encoding checks: we now correctly forbid: * VMOV-to-gpr with U:opc1:opc2 == 10x00 or x0x10 * VMOV-from-gpr with opc1:opc2 == 0x10 * VDUP with B:E == 11 * VDUP with Q == 1 and Vn<0> == 1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- The accesses of elements < 32 bits could be improved by doing direct ld/st of the right size rather than 32-bit read-and-shift or read-modify-write, but we leave this for later cleanup, since this series is generally trying to stick to fixing the decode. Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Add helpers for VFP register loads and storesPeter Maydell2-20/+30
The current VFP code has two different idioms for loading and storing from the VFP register file: 1 using the gen_mov_F0_vreg() and similar functions, which load and store to a fixed set of TCG globals cpu_F0s, CPU_F0d, etc 2 by direct calls to tcg_gen_ld_f64() and friends We want to phase out idiom 1 (because the use of the fixed globals is a relic of a much older version of TCG), but idiom 2 is quite longwinded: tcg_gen_ld_f64(tmp, cpu_env, vfp_reg_offset(true, reg)) requires us to specify the 64-bitness twice, once in the function name and once by passing 'true' to vfp_reg_offset(). There's no guard against accidentally passing the wrong flag. Instead, let's move to a convention of accessing 64-bit registers via the existing neon_load_reg64() and neon_store_reg64(), and provide new neon_load_reg32() and neon_store_reg32() for the 32-bit equivalents. Implement the new functions and use them in the code in translate-vfp.inc.c. We will convert the rest of the VFP code as we do the decodetree conversion in subsequent commits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Move the VFP trans_* functions to translate-vfp.inc.cPeter Maydell2-337/+337
Move the trans_*() functions we've just created from translate.c to translate-vfp.inc.c. This is pure code motion with no textual changes (this can be checked with 'git show --color-moved'). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetreePeter Maydell2-39/+39
Convert the VCVTA/VCVTN/VCVTP/VCVTM instructions to decodetree. trans_VCVT() is temporarily left in translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetreePeter Maydell2-22/+43
Convert the VRINTA/VRINTN/VRINTP/VRINTM instructions to decodetree. Again, trans_VRINT() is temporarily left in translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VMINNM, VMAXNM to decodetreePeter Maydell2-13/+33
Convert the VMINNM and VMAXNM instructions to decodetree. As with VSEL, we leave the trans_VMINMAXNM() function in translate.c for the moment. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert the VSEL instructions to decodetreePeter Maydell4-10/+59
Convert the VSEL instructions to decodetree. We leave trans_VSEL() in translate.c for now as this allows the patch to show just the changes from the old handle_vsel(). In the old code the check for "do D16-D31 exist" was hidden in the VFP_DREG macro, and assumed that VFPv3 always implied that D16-D31 exist. In the new code we do the correct ID register test. This gives identical behaviour for most of our CPUs, and fixes previously incorrect handling for Cortex-R5F, Cortex-M4 and Cortex-M33, which all implement VFPv3 or better with only 16 double-precision registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu maxPeter Maydell1-0/+4
At the moment our -cpu max for AArch32 supports VFP short-vectors because we always implement them, even for CPUs which should not have them. The following commits are going to switch to using the correct ID-register-check to enable or disable short vector support, so we need to turn it on explicitly for -cpu max, because Cortex-A15 doesn't implement it. We don't enable this for the AArch64 -cpu max, because the v8A architecture never supports short-vectors. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Fix Cortex-R5F MVFR valuesPeter Maydell1-0/+2
The Cortex-R5F initfn was not correctly setting up the MVFR ID register values. Fill these in, since some subsequent patches will use ID register checks rather than CPU feature bit checks. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Factor out VFP access checking codePeter Maydell2-88/+113
Factor out the VFP access checking code so that we can use it in the leaf functions of the decodetree decoder. We call the function full_vfp_access_check() so we can keep the more natural vfp_access_check() for a version which doesn't have the 'ignore_vfp_enabled' flag -- that way almost all VFP insns will be able to use vfp_access_check(s) and only the special-register access function will have to use full_vfp_access_check(s, ignore_vfp_enabled). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Add stubs for AArch32 VFP decodetreePeter Maydell5-0/+119
Add the infrastructure for building and invoking a decodetree decoder for the AArch32 VFP encodings. At the moment the new decoder covers nothing, so we always fall back to the existing hand-written decode. We need to have one decoder for the unconditional insns and one for the conditional insns, as otherwise the patterns for conditional insns would incorrectly match against the unconditional ones too. Since translate.c is over 14,000 lines long and we're going to be touching pretty much every line of the VFP code as part of the decodetree conversion, we create a new translate-vfp.inc.c to hold the code which deals with VFP in the new scheme. It should be possible to convert this into a standalone translation unit eventually, but the conversion process will be much simpler if we simply #include it midway through translate.c to start with. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13decodetree: Fix comparison of FieldRichard Henderson1-1/+1
Typo comparing the sign of the field, twice, instead of also comparing the mask of the field (which itself encodes both position and length). Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190604154225.26992-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13target/arm: Fix output of PAuth AuthRichard Henderson3-3/+64
The ARM pseudocode installs the error_code into the original pointer, not the encrypted pointer. The difference applies within the 7 bits of pac data; the result should be the sign extension of bit 55. Add a testcase to that effect. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13hw/core/bus.c: Only the main system bus can have no parentPeter Maydell1-12/+9
In commit 80376c3fc2c38fdd453 in 2010 we added a workaround for some qbus buses not being connected to qdev devices -- if the bus has no parent object then we register a reset function which resets the bus on system reset (and unregister it when the bus is unparented). Nearly a decade later, we have now no buses in the tree which are created with non-NULL parents, so we can remove the workaround and instead just assert that if the bus has a NULL parent then it is the main system bus. (The absence of other parentless buses was confirmed by code inspection of all the callsites of qbus_create() and qbus_create_inplace() and cross-checked by 'make check'.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190523150543.22676-1-peter.maydell@linaro.org
2019-06-13hw/arm/smmuv3: Fix decoding of ID register rangePeter Maydell1-1/+1
The SMMUv3 ID registers cover an area 0x30 bytes in size (12 registers, 4 bytes each). We were incorrectly decoding only the first 0x20 bytes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20190524124829.2589-1-peter.maydell@linaro.org
2019-06-13target/arm: Implement NSACR gating of floating pointPeter Maydell1-2/+73
The NSACR register allows secure code to configure the FPU to be inaccessible to non-secure code. If the NSACR.CP10 bit is set then: * NS accesses to the FPU trap as UNDEF (ie to NS EL1 or EL2) * CPACR.{CP10,CP11} behave as if RAZ/WI * HCPTR.{TCP11,TCP10} behave as if RAO/WI Note that we do not implement the NSACR.NSASEDIS bit which gates only access to Advanced SIMD, in the same way that we don't implement the equivalent CPACR.ASEDIS and HCPTR.TASE. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190510110357.18825-1-peter.maydell@linaro.org
2019-06-13target/arm: Use tcg_gen_gvec_bitselRichard Henderson4-78/+20
This replaces 3 target-specific implementations for BIT, BIF, and BSL. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190518191934.21887-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13Merge remote-tracking branch 'remotes/kraxel/tags/vga-20190613-pull-request' ↵Peter Maydell5-6/+14
into staging edid: add xmax + ymax properties, enable by default. # gpg: Signature made Thu 13 Jun 2019 08:38:18 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20190613-pull-request: edid: flip the default to enabled edid: add xmax + ymax properties Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190612' into stagingPeter Maydell1-3/+3
Fix vector arithmetic right shift helpers. # gpg: Signature made Thu 13 Jun 2019 05:10:11 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190612: tcg: Fix typos in helper_gvec_sar{8,32,64}v Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2019-06-12' into ↵Peter Maydell42-59/+447
staging QAPI patches for 2019-06-12 # gpg: Signature made Wed 12 Jun 2019 17:44:50 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2019-06-12: qapi: Simplify how QAPIDoc implements its state machine file-posix: Add dynamic-auto-read-only QAPI feature qapi: Allow documentation for features qapi: Disentangle QAPIDoc code tests/qapi-schema: Error case tests for features in structs tests/qapi-schema: Test for good feature lists in structs qapi: Add feature flags to struct types block/gluster: update .help of BLOCK_OPT_PREALLOC option block/file-posix: update .help of BLOCK_OPT_PREALLOC option qapi/block-core: update documentation of preallocation parameter qdev: Delete unused LostTickPolicy "merge" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13ui/cocoa: Fix mouse grabbing in fullscreen mode for relative input deviceChen Zhang1-1/+6
In fullscreen mode, the window property of cocoaView may not be the key window, and the current implementation would not re-grab cursor by left click in fullscreen mode after ungrabbed in fullscreen mode with hot-key ctrl-opt-g. This patch used value of isFullscreen as a short-cirtuit condition for relative input device grabbing. Signed-off-by: Chen Zhang <tgfbeta@me.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 2D2F1191-E82F-4B54-A6E7-73FFB953DE93@me.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13ui/cocoa: Fix absolute input device grabbing issue on MojaveChen Zhang1-2/+41
On Mojave, absolute input device, i.e. tablet, had trouble re-grabbing the cursor in re-entry into the virtual screen area. In some cases, the `window` property of NSEvent object was nil after cursor exiting from window, hinting that the `-locationInWindow` method would return value in screen coordinates. The current implementation used raw locations from NSEvent without considering whether the value was for the window coordinates or the macOS screen coordinates, nor the zooming factor for Zoom-to-Fit in fullscreen mode. In fullscreen mode, the fullscreen cocoa window might not be the key window, therefore the location of event in virtual coordinates should suffice. This patches fixed boundary check methods for cursor in normal and fullscreen with/without Zoom-to-Fit in Mojave. Note: CGRect, -convertRectToScreen: and -convertRectFromScreen: were used in coordinates conversion for compatibility reason. Signed-off-by: Chen Zhang <tgfbeta@me.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: FA3FBC4F-5379-4118-B997-58FE05CC58F9@me.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13Merge remote-tracking branch ↵Peter Maydell22-607/+1788
'remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3' into staging Various fixes and updates: - editor config tweak for shell scripts - iotest updates (still not default for make check) - various docker updates - gcc/ubsan updates for travis - some clean-ups for tests/vm (no serial autoinstall) - semihosting fix for Coverity - fixes for cputlb in 64-on-32 cases - gdbstub re-factor + maintainership update # gpg: Signature made Wed 12 Jun 2019 17:55:04 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-gdbstub-cputlb-120619-3: (40 commits) gdbstub: Implement qemu physical memory mode gdbstub: Clear unused variables in gdb_handle_packet gdbstub: Implement target halted (? pkt) with new infra gdbstub: Implement generic set/query (Q/q pkt) with new infra gdbstub: Implement v commands with new infra gdbstub: Implement step (s pkt) with new infra gdbstub: Implement file io (F pkt) with new infra gdbstub: Implement read all registers (g pkt) with new infra gdbstub: Implement write all registers (G pkt) with new infra gdbstub: Implement read memory (m pkt) with new infra gdbstub: Implement write memory (M pkt) with new infra gdbstub: Implement get register (p pkt) with new infra gdbstub: Implement set register (P pkt) with new infra gdbstub: Implement breakpoint commands (Z/z pkt) with new infra gdbstub: Implement set_thread (H pkt) with new infra gdbstub: Implement continue with signal (C pkt) with new infra gdbstub: Implement continue (c pkt) with new infra gdbstub: Implement thread_alive (T pkt) with new infra gdbstub: Implement deatch (D pkt) with new infra gdbstub: Add infrastructure to parse cmd packets ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-13edid: flip the default to enabledGerd Hoffmann4-5/+11
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 20190607083444.32175-1-kraxel@redhat.com
2019-06-13edid: add xmax + ymax propertiesGerd Hoffmann1-1/+3
Add new properties to allow setting the maximum display resolution. Resolutions larger than that will not be included in the mode list. In linux guests xrandr can be used to list modes. Note: The existing xres and yres properties set the preferred display resolution, i.e. the mode should be first in the mode list and guests should use it by default. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20190607083429.31943-1-kraxel@redhat.com
2019-06-12tcg: Fix typos in helper_gvec_sar{8,32,64}vRichard Henderson1-3/+3
The loop is written with scalars, not vectors. Use the correct type when incrementing. Fixes: 5ee5c14cacd Reported-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-12gdbstub: Implement qemu physical memory modeJon Doron1-2/+60
Add a new query/set which changes the memory GDB sees to physical memory only. gdb> maint packet qqemu.PhyMemMode will reply the current phy_mem_mode state (1 for enabled, 0 for disabled) gdb> maint packet Qqemu.PhyMemMode:1 Will make GDB read/write only to physical memory, set to 0 to disable Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-21-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Clear unused variables in gdb_handle_packetJon Doron1-9/+2
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-20-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement target halted (? pkt) with new infraJon Doron1-10/+25
Note: The user-mode thread-id has been correctly reported since bd88c780e6 Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-19-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement generic set/query (Q/q pkt) with new infraJon Doron1-186/+373
The generic set/query packets contains implementation for varioius sub-commands which are required for GDB and also additional commands which are QEMU specific. To see which QEMU specific commands are available use the command gdb> maintenance packet qqemu.Supported Currently the only implemented QEMU specific command is the command that sets the single step behavior. gdb> maintenance packet qqemu.sstepbits Will display the MASK bits used to control the single stepping. gdb> maintenance packet qqemu.sstep Will display the current value of the mask used when single stepping. gdb> maintenance packet Qqemu.sstep:HEX_VALUE Will change the single step mask. Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-18-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement v commands with new infraJon Doron1-60/+110
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-17-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement step (s pkt) with new infraJon Doron1-6/+19
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-16-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement file io (F pkt) with new infraJon Doron1-22/+26
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-15-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement read all registers (g pkt) with new infraJon Doron1-8/+23
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-14-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement write all registers (G pkt) with new infraJon Doron1-10/+31
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-13-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement read memory (m pkt) with new infraJon Doron1-16/+32
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-12-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement write memory (M pkt) with new infraJon Doron1-18/+33
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-11-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement get register (p pkt) with new infraJon Doron1-12/+38
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-10-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement set register (P pkt) with new infraJon Doron1-9/+30
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-9-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement breakpoint commands (Z/z pkt) with new infraJon Doron1-19/+67
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-8-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement set_thread (H pkt) with new infraJon Doron1-30/+53
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-7-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement continue with signal (C pkt) with new infraJon Doron1-5/+29
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-6-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement continue (c pkt) with new infraJon Doron1-6/+19
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-5-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement thread_alive (T pkt) with new infraJon Doron1-11/+32
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-4-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Implement deatch (D pkt) with new infraJon Doron1-40/+61
Signed-off-by: Jon Doron <arilou@gmail.com> Message-Id: <20190529064148.19856-3-arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12gdbstub: Add infrastructure to parse cmd packetsJon Doron1-0/+195
Signed-off-by: Jon Doron <arilou@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20190529064148.19856-2-arilou@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2019-06-12cputlb: cast size_t to target_ulong before using for address masksAlex Bennée1-1/+1
While size_t is defined to happily access the biggest host object this isn't the case when generating masks for 64 bit guests on 32 bit hosts. Otherwise we end up truncating the address when we fall back to our unaligned helper. Fixes: https://bugs.launchpad.net/qemu/+bug/1831545 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Andrew Randrianasulu <randrianasulu@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
generated by cgit v1.1 at 2025-01-14 04:58:32 +0000