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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-06-11 16:39:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-06-13 15:14:03 +0100 |
| commit | 3de79d335c9aa7d726865e3933d9b21781032183 (patch) | |
| tree | 3ee701ec80e013f8c3e3e5afe6fb66da97c4083a | |
| parent | 06db8196bba34776829020192ed623a0b22e6557 (diff) | |
| download | qemu-3de79d335c9aa7d726865e3933d9b21781032183.zip qemu-3de79d335c9aa7d726865e3933d9b21781032183.tar.gz qemu-3de79d335c9aa7d726865e3933d9b21781032183.tar.bz2 | |
target/arm: Fix Cortex-R5F MVFR values
The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
| -rw-r--r-- | target/arm/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 4d5d46d..c8441fc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1609,6 +1609,8 @@ static void cortex_r5f_initfn(Object *obj) cortex_r5_initfn(obj); set_feature(&cpu->env, ARM_FEATURE_VFP3); + cpu->isar.mvfr0 = 0x10110221; + cpu->isar.mvfr1 = 0x00000011; } static const ARMCPRegInfo cortexa8_cp_reginfo[] = { |