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2025-02-13rust: callbacks: allow passing optional callbacks as ()Paolo Bonzini1-0/+97
In some cases, callbacks are optional. Using "Some(function)" and "None" does not work well, because when someone writes "None" the compiler does not know what to use for "F" in "Option<F>". Therefore, adopt () to mean a "null" callback. It is possible to enforce that a callback is valid by adding a "let _: () = F::ASSERT_IS_SOME" before the invocation of F::call. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-13rust: qom: add object creation functionalityPaolo Bonzini4-34/+48
The basic object lifecycle test can now be implemented using safe code! Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-13rust: qom: add reference counting functionalityPaolo Bonzini3-7/+178
Add a smart pointer that allows to add and remove references from QOM objects. It's important to note that while all QOM objects have a reference count, in practice not all of them have their lifetime guarded by it. Embedded objects, specifically, are confined to the lifetime of the owner. When writing Rust bindings this is important, because embedded objects are *never* used through the "Owned<>" smart pointer that is introduced here. Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-13rust: docs: document naming conventionPaolo Bonzini1-0/+44
As agreed in the "vtables and procedural macros" thread on the mailing list. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-02-12Merge tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu into ↵Stefan Hajnoczi6-563/+584
staging loongarch queue # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ6wQngAKCRAfewwSUazn # 0SggAQDk5mp90dBJwu05kioq+Inx/bwxmamweA+FmeqAnoQ79QEApDBPfppkrN2y # AxNZL0EL5zRFU3zECSTevpRMQ3UoVQk= # =tLFD # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 22:08:14 EST # gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1 # gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C # Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1 * tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu: hw/loongarch/virt: CPU irq line connection improvement hw/loongarch/virt: Remove unused ipistate hw/loongarch/virt: Set iocsr address space when CPU is created hw/loongarch/virt: Add separate file for fdt building hw/loongarch/virt: Rename function prefix name hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-12Merge tag 'pull-nbd-2025-02-11' of https://repo.or.cz/qemu/ericb into stagingStefan Hajnoczi6-28/+64
NBD patches for 2025-02-11 - Add --handshake-limit option to qemu-nbd # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEccLMIrHEYCkn0vOqp6FrSiUnQ2oFAmersd8ACgkQp6FrSiUn # Q2pDUAf/c7inV7W+9vQv15lZoadIJkXAhqu+j1YuITC52gMgmU1QcwXMXRPEak4V # qEIodiInzOtktMRXr6tbMroQgqo9eNd+VivxVa+J5LBILuZwdpZnLxsVNjblhbfI # R3swWs2qluh9/1czntRu0J+YVOj3YZnF86Z5+iwEdLQ+i15dtjXDirBRvGCd6miV # HLiEXwHdyPYb4g50a5oZCf3HhqPOgXOd+NWr4ifGut3bDulQk+FMDeBwV6/fmRPw # g7dFPHMrAEYMw8tScYTMCoZGSZl0lg1JNuSh/WwgXx7BgXtDDxyP4HaAXlIyOHIA # FbPU6aNrGZ9EDN4NA688IwUDh+lkmQ== # =WyjJ # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 15:23:59 EST # gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full] # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full] # gpg: aka "[jpeg image of size 6874]" [full] # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * tag 'pull-nbd-2025-02-11' of https://repo.or.cz/qemu/ericb: nbd/server: Allow users to adjust handshake limit in QMP qemu-nbd: Allow users to adjust handshake limit Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-12Merge tag 'pull-target-arm-20250211' of ↵Stefan Hajnoczi37-714/+2330
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * target/alpha: Don't corrupt error_code with unknown softfloat flags * target/arm: Implement FEAT_AFP and FEAT_RPRES # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmereaQZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gyLEACglOM4E0j1hRl/JZlWD384 # nZL01Hayp9xwSNn28hkXaajCxkErTWLuCZax1g1fBvt/Yqn+E3oFan8gIybMEVgK # 9ei6/m45fuICSQQhifvYTtYhAMd5uclr0anjRp9gN7FH6aaNPan/ZQYcKYxFq6cp # RDTF5qiHIgTeXAlU+WiioxravL3A/D+jcQMYLEI5L+Vt5nYNM589PSNFWNLQ6W9e # Gtmvp0uzrRSZgWxR3nOvhsn1NS/xXK90Zil+GPBo4jf82QVumqKYMsAcireOlxfk # zTlHXH3PuonGj/ZPLxmiVKYhLb1RglQ9kIs/FHVel18QTz4dJ3DaJp8QXCNHbrKz # 3aUwSiIh5Y/s3Q/X2Qy3jUHQ5tSjayhIhGFbn6zPdZ+2JZbIEu1Czeparddu/Zlq # OR0CMVo2Lj/C6OakEU1/YRTKBKiNBaN1eVHi7gjzTDBdbMMC7ZlNuimpFAbthmSC # szHzkgX8LXHzJqe4vip27yOMFBRPxvst/CXcEoPnjsLEQhLlKjOeFiHuEI+DUvaI # 24AJ5b0FDdSOEcaFkxFD6gxW8E77MiNtBncfxDxTMKHs/4yFGiDihSPnOCANn3Kk # zpQIwl0KJAPTA6Cldck9lY7MsKgGPTUNhEThadZlInbp4Uc6T1bvNDtB9b7osDfy # FeposcM1+GBeuSde0yD6oQ== # =P3wv # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 11:24:04 EST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250211' of https://git.linaro.org/people/pmaydell/qemu-arm: (68 commits) target/arm: Sink fp_status and fpcr access into do_fmlal* target/arm: Read fz16 from env->vfp.fpcr target/arm: Simplify DO_VFP_cmp in vfp_helper.c target/arm: Simplify fp_status indexing in mve_helper.c target/arm: Remove fp_status_a32 target/arm: Remove fp_status_a64 target/arm: Remove fp_status_f16_a32 target/arm: Remove fp_status_f16_a64 target/arm: Remove ah_fp_status target/arm: Remove ah_fp_status_f16 target/arm: Remove standard_fp_status target/arm: Remove standard_fp_status_f16 target/arm: Introduce CPUARMState.vfp.fp_status[] target/arm: Enable FEAT_RPRES for -cpu max target/arm: Implement increased precision FRSQRTE target/arm: Implement increased precision FRECPE target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper target/arm: Enable FEAT_AFP for '-cpu max' target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors) target/arm: Handle FPCR.AH in SVE FMLSL (indexed) ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-12Merge tag 'pull-vfio-20250211' of https://github.com/legoater/qemu into stagingStefan Hajnoczi12-165/+177
vfio queue: * Coverity fix * IGD cleanups using VFIOQuirk * SIGSEV fix in IOMMUFD host IOMMU device * Improved error reporting for MMIO region mapping failures # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmerTzQACgkQUaNDx8/7 # 7KHXLw/+LaONyFor+kuorb5et6rzyrE4keIUDv8zDTM4FnwFKP31wX8feQ63o17U # DQUYN4uM5Ah/PemF/IBCj44x1Eirzl8LW51sMtxg/weCa8xrZOsHjmoKNml4f+zs # ERzO/KSu9PWEWEyX79XGCcu5VQKl60b8Ra5QMBNKZKjVZpfBTxCjHZFIvQxSJFvm # gPKHFDtmtbhtBnq3U/N/PwpnUuH4+p6ofz1eKdOcin11CAks7cAt6bl1CIs7sUbC # ttrrQg6D+UJ5b+ISZjsw5hakfRIdtlZ/lS4jk678gN06108CIMmFPLPaRu27mdX9 # 4wBiMSQM8fFbbHw66FQiPgJeeGAmG/PvdLN4SbRSujkEkKyEyqtH2dRINy9PNXj4 # ZXXugx7xqfPfTEC1lwsyGDdHdHH022V0ScdDpx+K87klRvu30ZjorB7QSCI7x+ZN # yW2ztZQ2hNH6MsgrKTQS6MLArHgU+h0ycaHy+01jj5UKSs3xAf53wNnx2uoBmKGj # gZB/tNFg60qeSuW900ybnBTaH60qLs6xzY7evDRa5cqPYJ+z/lRUYp45fmsgQ1yR # 91PHhC/mQLFjQRc78vF6k7slMm/Fk8JOalZgYPtm+Atdw3ufjOexavoHqN3Sa1Us # keKnR589kHikPd3zZN7sZzT8wMNTAcRbSy72360+PzEZ1Iiiu+M= # =wpSw # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 08:23:00 EST # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20250211' of https://github.com/legoater/qemu: vfio: Remove superfluous error report in vfio_listener_region_add() vfio: Remove reports of DMA mapping errors in backends vfio: Improve error reporting when MMIO region mapping fails vfio: Introduce vfio_get_vfio_device() vfio: Rephrase comment in vfio_listener_region_add() error path vfio/pci: Replace "iommu_device" by "vIOMMU" util/error: Introduce warn_report_err_once() vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach() vfio/igd: use VFIOConfigMirrorQuirk for mirrored registers vfio/pci: introduce config_offset field in VFIOConfigMirrorQuirk vfio/pci: declare generic quirks in a new header file vfio/igd: Fix potential overflow in igd_gtt_memory_size() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-12hw/loongarch/virt: CPU irq line connection improvementBibo Mao2-24/+38
Interrupt controller extioi and ipi connect to CPU with irq line method. With command -smp x, -device la464-loongarch-cpu, smp.cpus is not accurate for all possible CPU objects, possible_cpu_arch_ids() is used. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-02-12hw/loongarch/virt: Remove unused ipistateBibo Mao2-7/+0
Field ipistate in LoongArch CPU object is not used any more, remove it here. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-02-12hw/loongarch/virt: Set iocsr address space when CPU is createdBibo Mao1-1/+1
There is only one iocsr address space for the whole virt-machine board. When CPU is created, the one of percpu points to that of the board. Here set iocsr address space when CPU is created rather than IPI creation stage. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn>
2025-02-12hw/loongarch/virt: Add separate file for fdt buildingBibo Mao4-525/+539
Similiar with virt-acpi-build.c, file virt-fdt-build.c is added here. And move functions relative with fdt table building to the file. It is only code movement and there is no function change. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-12hw/loongarch/virt: Rename function prefix nameBibo Mao3-5/+5
Replace function prefix name loongarch_xxx with virt_xxx in file virt-acpi-build.c Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-12hw/loongarch/virt: Rename filename acpi-build with virt-acpi-buildBibo Mao2-1/+1
File acpi-build.c is relative with virt machine type, rename it with virt-acpi-build.c Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2025-02-11nbd/server: Allow users to adjust handshake limit in QMPEric Blake4-13/+33
Although defaulting the handshake limit to 10 seconds was a nice QoI change to weed out intentionally slow clients, it can interfere with integration testing done with manual NBD_OPT commands over 'nbdsh --opt-mode'. Expose a QMP knob 'handshake-max-secs' to allow the user to alter the timeout away from the default. The parameter name here intentionally matches the spelling of the constant added in commit fb1c2aaa98, and not the command-line spelling added in the previous patch for qemu-nbd; that's because in QMP, longer names serve as good self-documentation, and unlike the command line, machines don't have problems generating longer spellings. Signed-off-by: Eric Blake <eblake@redhat.com> Message-ID: <20250203222722.650694-6-eblake@redhat.com> [eblake: s/max-secs/max-seconds/ in QMP] Acked-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
2025-02-11qemu-nbd: Allow users to adjust handshake limitEric Blake2-15/+31
Although defaulting the handshake limit to 10 seconds was a nice QoI change to weed out intentionally slow clients, it can interfere with integration testing done with manual NBD_OPT commands over 'nbdsh --opt-mode'. Expose a command line option to allow the user to alter the timeout away from the default. This option is unlikely to be used in enough scenarios to warrant a short option letter. The option --handshake-limit intentionally differs from the name of the constant added in commit fb1c2aaa98 (limit instead of max_secs) and the QMP name to be added in the next commit; this is because typing a longer command-line name is undesirable and there is sufficient --help text to document the units. Signed-off-by: Eric Blake <eblake@redhat.com> Message-ID: <20250203222722.650694-5-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
2025-02-11Merge tag 'pull-request-2025-02-11' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi10-187/+228
staging * Convert more avocado tests to the functional framework * Add a test for the sam460ex machine * Fix the broken FreeBSD CI job by updating it to the latest version # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmerQmoRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUTeg/+OKvhapE34jUJTQhDkB0XFbFsdhKx/0Jq # UDL435i49B/x68t4sogZrg1qdYHrwANiTwsH/g0llX31oguENLdidUkvS3PhFbMo # QqxfjdlrLwOia1P3/KlWJ9KbxoXmXccDH+LoANoHzO0NPg21tLNPbUUexaouIAvc # ynvQV/OPS5bQRJCrIFN6PbQ6lyYcTOuJJU7j5Vr6FcqKmg7OH9IBCXHmcyEIFCki # Zh/99+IDQkdWWVVsRSkLEPmXGKI/EasPC2GMTQ0LvztkqFUpycufOaL3Qz06yqMP # ZxfshsKfOGCMOMClePICPrck4uvhuMoeXszrjsCWArOYzumuN5al4MtXLJZLWs92 # p+nk0XGQmxjdCHj2ip/lasdjwPd2L1pk4+MXHBUgrmwgDo6EUW55DJd/E8ORsEY9 # yvV4CCL3nCX2PRO1eUgo5FPhQbwF2TgLQO6ut69yRsVzcXh2w/Thzc++eH/qhCYI # fbZUoIySfCcNLzDK/E5H3YVSQHvkc8cE3ymkb1BAOepVkdadc2l0P0D4RmO0/Nxk # vy30Ik5+bf6xsJjpiYFQi8NwGNUwZlDPqlWikVWotlOhobmOqVIlnCovQ06mnru3 # wsneISRLctPMHjlU6u1iuDiO0LG1CUvXrbP01mDwgGXaYAWg7o2e7rlbrExDHzwu # fRs2aYnR9oY= # =K10z # -----END PGP SIGNATURE----- # gpg: Signature made Tue 11 Feb 2025 07:28:26 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-02-11' of https://gitlab.com/thuth/qemu: gitlab-ci.d/cirrus: Update the FreeBSD job to v14.2 gitlab: use new(ish) cirrus-vars command for creating config gitlab: don't fail cirrus CI jobs when credits are exhausted tests/functional: Add a ppc sam460ex test tests/functional: Convert the hotplug_blk avocado test tests/functional/test_aarch64_virt: Fix vulkan test without egl-headless tests/functional: Convert the aarch64 xen test to the functional framework Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-02-11target/arm: Sink fp_status and fpcr access into do_fmlal*Richard Henderson1-12/+16
Sink common code from the callers into do_fmlal and do_fmlal_idx. Reorder the arguments to minimize the re-sorting from the caller's arguments. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-35-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Read fz16 from env->vfp.fpcrRichard Henderson1-6/+6
Read the bit from the source, rather than from the proxy via get_flush_inputs_to_zero. This makes it clear that it does not matter which of the float_status structures is used. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-34-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Simplify DO_VFP_cmp in vfp_helper.cRichard Henderson1-5/+5
Pass ARMFPStatusFlavour index instead of fp_status[FOO]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Simplify fp_status indexing in mve_helper.cRichard Henderson1-26/+14
Select on index instead of pointer. No functional change. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove fp_status_a32Richard Henderson4-17/+12
Replace with fp_status[FPST_A32]. As this was the last of the old structures, we can remove the anonymous union and struct. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-15-richard.henderson@linaro.org [PMM: tweak to account for change to is_ebf()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove fp_status_a64Richard Henderson5-16/+15
Replace with fp_status[FPST_A64]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove fp_status_f16_a32Richard Henderson4-11/+10
Replace with fp_status[FPST_A32_F16]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove fp_status_f16_a64Richard Henderson5-16/+14
Replace with fp_status[FPST_A64_F16]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove ah_fp_statusRichard Henderson3-8/+7
Replace with fp_status[FPST_AH]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove ah_fp_status_f16Richard Henderson3-8/+7
Replace with fp_status[FPST_AH_F16]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove standard_fp_statusRichard Henderson5-23/+22
Replace with fp_status[FPST_STD]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Remove standard_fp_status_f16Richard Henderson4-19/+18
Replace with fp_status[FPST_STD_F16]. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Introduce CPUARMState.vfp.fp_status[]Richard Henderson2-114/+71
Move ARMFPStatusFlavour to cpu.h with which to index this array. For now, place the array in an anonymous union with the existing structures. Adjust the order of the existing structures to match the enum. Simplify fpstatus_ptr() using the new array. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250129013857.135256-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Enable FEAT_RPRES for -cpu maxPeter Maydell2-0/+2
Now the emulation is complete, we can enable FEAT_RPRES for the 'max' CPU type. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Implement increased precision FRSQRTEPeter Maydell1-13/+64
Implement the increased precision variation of FRSQRTE. In the pseudocode this corresponds to the handling of the "increasedprecision" boolean in the FPRSqrtEstimate() and RecipSqrtEstimate() functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Implement increased precision FRECPEPeter Maydell1-8/+46
Implement the increased precision variation of FRECPE. In the pseudocode this corresponds to the handling of the "increasedprecision" boolean in the FPRecipEstimate() and RecipEstimate() functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helperPeter Maydell6-8/+85
FEAT_RPRES implements an "increased precision" variant of the single precision FRECPE and FRSQRTE instructions from an 8 bit to a 12 bit mantissa. This applies only when FPCR.AH == 1. Note that the halfprec and double versions of these insns retain the 8 bit precision regardless. In this commit we add all the plumbing to make these instructions call a new helper function when the increased-precision is in effect. In the following commit we will provide the actual change in behaviour in the helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Enable FEAT_AFP for '-cpu max'Peter Maydell2-0/+2
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we can enable FEAT_AFP for '-cpu max', and document that we support it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)Richard Henderson1-3/+12
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE FMLSL (indexed), using the usual trick of negating by XOR when AH=0 and by muladd flags when AH=1. Since we have the CPUARMState* in the helper anyway, we can look directly at env->vfp.fpcr and don't need toa pass in the FPCR.AH value via the SIMD data word. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-33-richard.henderson@linaro.org [PMM: tweaked commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in SVE FMLSL (indexed)Richard Henderson1-3/+12
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE FMLSL (indexed), using the usual trick of negating by XOR when AH=0 and by muladd flags when AH=1. Since we have the CPUARMState* in the helper anyway, we can look directly at env->vfp.fpcr and don't need toa pass in the FPCR.AH value via the SIMD data word. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-32-richard.henderson@linaro.org [PMM: commit message tweaked] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in FMLSL (by element and vector)Richard Henderson1-25/+46
Handle FPCR.AH's requirement to not negate the sign of a NaN in FMLSL by element and vector, using the usual trick of negating by XOR when AH=0 and by muladd flags when AH=1. Since we have the CPUARMState* in the helper anyway, we can look directly at env->vfp.fpcr and don't need toa pass in the FPCR.AH value via the SIMD data word. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-31-richard.henderson@linaro.org [PMM: commit message tweaked] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in SVE FCMLARichard Henderson2-28/+43
The negation step in SVE FCMLA mustn't negate a NaN when FPCR.AH is set. Use the same approach as we did for A64 FCMLA of passing in FPCR.AH and using it to select whether to negate by XOR or by the muladd negate_product flag. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-28-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in FCMLA by indexRichard Henderson2-19/+27
The negation step in FCMLA by index mustn't negate a NaN when FPCR.AH is set. Use the same approach as vector FCMLA of passing in FPCR.AH and using it to select whether to negate by XOR or by the muladd negate_product flag. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-27-richard.henderson@linaro.org [PMM: Expanded commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in vector FCMLARichard Henderson2-28/+40
The negation step in FCMLA mustn't negate a NaN when FPCR.AH is set. Handle this by passing FPCR.AH to the helper via the SIMD data field, and use this to select whether to do the negation via XOR or via the muladd negate_product flag. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250129013857.135256-26-richard.henderson@linaro.org [PMM: Expanded commit message] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in SVE FTMADPeter Maydell2-10/+35
The negation step in the SVE FTMAD insn mustn't negate a NaN when FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field, so we can select the correct behaviour. Because the operand is known to be negative, negating the operand is the same as taking the absolute value. Defer this to the muladd operation via flags, so that it happens after NaN detection, which is correct for FPCR.AH. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in SVE FTSSELPeter Maydell2-5/+17
The negation step in the SVE FTSSEL insn mustn't negate a NaN when FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field and use that to determine whether to do the negation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in negation step in SVE FMLS (vector)Peter Maydell3-24/+114
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the SVE FMLS (vector) insns, by providing new helpers for the AH=1 case which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions that do the work. The float*_muladd functions have a flags argument that can perform optional negation of various operand. We don't use that for "normal" arm fmla, because the muladd flags are not applied when an input is a NaN. But since FEAT_AFP does not negate NaNs, this behaviour is exactly what we need. The non-AH helpers pass in a zero flags argument and control the negation via the neg1 and neg3 arguments; the AH helpers always pass in neg1 and neg3 as zero and control the negation via the flags argument. This allows us to avoid conditional branches within the inner loop. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in negation in FMLS (vector)Peter Maydell3-1/+32
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS (vector), by implementing a new set of helpers for the AH=1 case. The float_muladd_negate_product flag produces the same result as negating either of the multiplication operands, assuming neither of the operands are NaNs. But since FEAT_AFP does not negate NaNs, this behaviour is exactly what we need. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in negation step in FMLS (indexed)Peter Maydell4-29/+57
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS (indexed). We do this by creating 6 new helpers, which allow us to do the negation either by XOR (for AH=0) or by muladd flags (for AH=1). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> [PMM: Mostly from RTH's patch; error in index order into fns[][] fixed] Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insnsPeter Maydell4-6/+44
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in the vector versions of FRECPS and FRSQRTS, by implementing new vector wrappers that call the _ah_ scalar helpers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insnsPeter Maydell4-82/+84
Handle the FPCR.AH semantics that we do not change the sign of an input NaN in the FRECPS and FRSQRTS scalar insns, by providing new helper functions that do the CHS part of the operation differently. Since the extra helper functions would be very repetitive if written out longhand, we condense them and the existing non-AH helpers into being emitted via macros. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in negation steps in FCADDPeter Maydell2-26/+38
The negation steps in FCADD must honour FPCR.AH's "don't change the sign of a NaN" semantics. Implement this by encoding FPCR.AH into the SIMD data field passed to the helper and using that to decide whether to negate the values. The construction of neg_imag and neg_real were done to make it easy to apply both in parallel with two simple logical operations. This changed with FPCR.AH, which is more complex than that. Switch to an approach closer to the pseudocode, where we extract the rot parameter from the SIMD data word and negate the appropriate input value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2025-02-11target/arm: Handle FPCR.AH in negation steps in SVE FCADDPeter Maydell3-13/+48
The negation steps in FCADD must honour FPCR.AH's "don't change the sign of a NaN" semantics. Implement this in the same way we did for the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field passed to the helper and using that to decide whether to negate the values. The construction of neg_imag and neg_real were done to make it easy to apply both in parallel with two simple logical operations. This changed with FPCR.AH, which is more complex than that. Switch to an approach that follows the pseudocode more closely, by extracting the 'rot=1' parameter from the SIMD data field and changing the sign of the appropriate input value. Note that there was a naming issue with neg_imag and neg_real. They were named backward, with neg_imag being non-zero for rot=1, and vice versa. This was combined with reversed usage within the loop, so that the negation in the end turned out correct. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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