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2024-11-04qemu-ga: Fix a SIGSEGV in ga_run_command() helperSunil Nimmagadda1-1/+1
qemu-ga on a NetBSD -current VM terminates with a SIGSEGV upon receiving 'guest-set-time' command... Core was generated by `qemu-ga'. Program terminated with signal SIGSEGV, Segmentation fault. #0 0x000000000cd37a40 in ga_pipe_read_str (fd=fd@entry=0xffffff922a20, str=str@entry=0xffffff922a18) at ../qga/commands-posix.c:88 88 *str[len] = '\0'; [Current thread is 1 (process 1112)] (gdb) bt #0 0x000000000cd37a40 in ga_pipe_read_str (fd=fd@entry=0xffffff922a20, str=str@entry=0xffffff922a18) at ../qga/commands-posix.c:88 #1 0x000000000cd37b60 in ga_run_command (argv=argv@entry=0xffffff922a90, action=action@entry=0xcda34b8 "set hardware clock to system time", errp=errp@entry=0xffffff922a70, in_str=0x0) at ../qga/commands-posix.c:164 #2 0x000000000cd380c4 in qmp_guest_set_time (has_time=<optimized out>, time_ns=<optimized out>, errp=errp@entry=0xffffff922ad0) at ../qga/commands-posix.c:304 #3 0x000000000cd253d8 in qmp_marshal_guest_set_time (args=<optimized out>, ret=<optimized out>, errp=0xffffff922b48) at qga/qga-qapi-commands.c:193 #4 0x000000000cd4e71c in qmp_dispatch (cmds=cmds@entry=0xcdf5b18 <ga_commands>, request=request@entry=0xf3c711a4b000, allow_oob=allow_oob@entry=false, cur_mon=cur_mon@entry=0x0) at ../qapi/qmp-dispatch.c:220 #5 0x000000000cd36524 in process_event (opaque=0xf3c711a79000, obj=0xf3c711a4b000, err=0x0) at ../qga/main.c:677 #6 0x000000000cd526f0 in json_message_process_token (lexer=lexer@entry=0xf3c711a79018, input=0xf3c712072480, type=type@entry=JSON_RCURLY, x=28, y=1) at ../qobject/json-streamer.c:99 #7 0x000000000cd93860 in json_lexer_feed_char (lexer=lexer@entry=0xf3c711a79018, ch=125 '}', flush=flush@entry=false) at ../qobject/json-lexer.c:313 #8 0x000000000cd93a00 in json_lexer_feed (lexer=lexer@entry=0xf3c711a79018, buffer=buffer@entry=0xffffff922d10 "{\"execute\":\"guest-set-time\"}\n", size=<optimized out>) at ../qobject/json-lexer.c:350 #9 0x000000000cd5290c in json_message_parser_feed (parser=parser@entry=0xf3c711a79000, buffer=buffer@entry=0xffffff922d10 "{\"execute\":\"guest-set-time\"}\n", size=<optimized out>) at ../qobject/json-streamer.c:121 #10 0x000000000cd361fc in channel_event_cb (condition=<optimized out>, data=0xf3c711a79000) at ../qga/main.c:703 #11 0x000000000cd3710c in ga_channel_client_event (channel=<optimized out>, condition=<optimized out>, data=0xf3c711b2d300) at ../qga/channel-posix.c:94 #12 0x0000f3c7120d9bec in g_main_dispatch () from /usr/pkg/lib/libglib-2.0.so.0 #13 0x0000f3c7120dd25c in g_main_context_iterate_unlocked.constprop () from /usr/pkg/lib/libglib-2.0.so.0 #14 0x0000f3c7120ddbf0 in g_main_loop_run () from /usr/pkg/lib/libglib-2.0.so.0 #15 0x000000000cda00d8 in run_agent_once (s=0xf3c711a79000) at ../qga/main.c:1522 #16 run_agent (s=0xf3c711a79000) at ../qga/main.c:1559 #17 main (argc=<optimized out>, argv=<optimized out>) at ../qga/main.c:1671 (gdb) The commandline options used on the host machine... qemu-system-aarch64 \ -machine type=virt,pflash0=rom \ -m 8G \ -cpu host \ -smp 8 \ -accel hvf \ -device virtio-net-pci,netdev=unet \ -device virtio-blk-pci,drive=hd \ -drive file=netbsd.qcow2,if=none,id=hd \ -netdev user,id=unet,hostfwd=tcp::2223-:22 \ -object rng-random,filename=/dev/urandom,id=viornd0 \ -device virtio-rng-pci,rng=viornd0 \ -serial mon:stdio \ -display none \ -blockdev node-name=rom,driver=file,filename=/opt/homebrew/Cellar/qemu/9.0.2/share/qemu/edk2-aarch64-code.fd,read-only=true \ -chardev socket,path=/tmp/qga_netbsd.sock,server=on,wait=off,id=qga0 \ -device virtio-serial \ -device virtconsole,chardev=qga0,name=org.qemu.guest_agent.0 This patch rectifies the operator precedence while assigning the NUL terminator. Fixes: c3f32c13a325f1ca9a0b08c19fefe9e5cc04289d Signed-off-by: Sunil Nimmagadda <sunil@nimmagadda.net> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Link: https://lore.kernel.org/r/m15xppk9qg.fsf@nimmagadda.net Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-04qga: fix missing static and prototypes windows warningsPierrick Bouvier3-6/+13
Reported by clang++, but not by g++. ../qga/vss-win32/provider.cpp:48:6: error: no previous prototype for function 'LockModule' [-Werror,-Wmissing-prototypes] 48 | void LockModule(BOOL lock) | ^ ../qga/vss-win32/provider.cpp:48:1: note: declare 'static' if the function is not intended to be used outside of this translation unit 48 | void LockModule(BOOL lock) | ^ | static ../qga/vss-win32/provider.cpp:531:13: error: no previous prototype for function 'DllMain' [-Werror,-Wmissing-prototypes] 531 | BOOL WINAPI DllMain(HINSTANCE hinstDll, DWORD dwReason, LPVOID lpReserved) | ^ ../qga/vss-win32/provider.cpp:531:1: note: declare 'static' if the function is not intended to be used outside of this translation unit 531 | BOOL WINAPI DllMain(HINSTANCE hinstDll, DWORD dwReason, LPVOID lpReserved) | ^ | static Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20241031040426.772604-7-pierrick.bouvier@linaro.org Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-04qga: fix -Wsometimes-uninitialized windows warningPierrick Bouvier1-1/+1
Reported by clang, but not gcc. [5123/5678] Compiling C object qga/qemu-ga.exe.p/commands-windows-ssh.c.obj FAILED: qga/qemu-ga.exe.p/commands-windows-ssh.c.obj "cc" "-Iqga/qemu-ga.exe.p" "-Iqga" "-I../qga" "-I." "-Iqapi" "-Itrace" "-Iui" "-Iui/shader" "-IC:/msys64/clangarm64/include/glib-2.0" "-IC:/msys64/clangarm64/lib/glib-2.0/include" "-fdiagnostics-color=auto" "-Wall" "-Winvalid-pch" "-Werror" "-std=gnu11" "-O2" "-g" "-fstack-protector-strong" "-Wempty-body" "-Wendif-labels" "-Wexpansion-to-defined" "-Wformat-security" "-Wformat-y2k" "-Wignored-qualifiers" "-Winit-self" "-Wmissing-format-attribute" "-Wmissing-prototypes" "-Wnested-externs" "-Wold-style-definition" "-Wredundant-decls" "-Wstrict-prototypes" "-Wtype-limits" "-Wundef" "-Wvla" "-Wwrite-strings" "-Wno-gnu-variable-sized-type-not-at-end" "-Wno-initializer-overrides" "-Wno-missing-include-dirs" "-Wno-psabi" "-Wno-shift-negative-value" "-Wno-string-plus-int" "-Wno-tautological-type-limit-compare" "-Wno-typedef-redefinition" "-Wthread-safety" "-iquote" "." "-iquote" "C:/w/qemu" "-iquote" "C:/w/qemu/include" "-iquote" "C:/w/qemu/host/include/aarch64" "-iquote" "C:/w/qemu/host/include/generic" "-iquote" "C:/w/qemu/tcg/aarch64" "-D_GNU_SOURCE" "-D_FILE_OFFSET_BITS=64" "-D_LARGEFILE_SOURCE" "-fno-strict-aliasing" "-fno-common" "-fwrapv" "-fno-pie" "-ftrivial-auto-var-init=zero" "-fzero-call-used-regs=used-gpr" -MD -MQ qga/qemu-ga.exe.p/commands-windows-ssh.c.obj -MF "qga/qemu-ga.exe.p/commands-windows-ssh.c.obj.d" -o qga/qemu-ga.exe.p/commands-windows-ssh.c.obj "-c" ../qga/commands-windows-ssh.c ../qga/commands-windows-ssh.c:383:9: error: variable 'userPSID' is used uninitialized whenever 'if' condition is true [-Werror,-Wsometimes-uninitialized] 383 | if (!create_acl(userInfo, &pACL, errp)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ../qga/commands-windows-ssh.c:415:15: note: uninitialized use occurs here 415 | LocalFree(userPSID); | ^~~~~~~~ ../qga/commands-windows-ssh.c:383:5: note: remove the 'if' if its condition is always false 383 | if (!create_acl(userInfo, &pACL, errp)) { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 384 | goto error; | ~~~~~~~~~~~ 385 | } | ~ ../qga/commands-windows-ssh.c:380:18: note: initialize the variable 'userPSID' to silence this warning 380 | PSID userPSID; | ^ | = NULL 1 error generated. Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com> Link: https://lore.kernel.org/r/20241031040426.772604-6-pierrick.bouvier@linaro.org Signed-off-by: Konstantin Kostiuk <kkostiuk@redhat.com>
2024-11-04aspeed: Don't set always boot properties of the emmc deviceCédric Le Goater1-3/+13
Commit e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") added support to boot from an eMMC device by setting the boot properties of the eMMC device. This change made the assumption that the device always has boot areas. However, if the machine boots from the flash device (or -kernel) and uses an eMMC device without boot areas, support would be broken. This impacts the ast2600-evb machine which can choose to boot from flash or eMMC using the "boot-emmc" machine option. To provide some flexibility for Aspeed machine users to use different flavors of eMMC devices (with or without boot areas), do not set the eMMC device boot properties when the machine is not configured to boot from eMMC. However, this approach makes another assumption about eMMC devices, namely that eMMC devices from which the machine does not boot do not have boot areas. A preferable alternative would be to add support for user creatable eMMC devices and define the device boot properties on the QEMU command line : -blockdev node-name=emmc0,driver=file,filename=mmc-ast2600-evb.raw \ -device emmc,bus=sdhci-bus.2,drive=emmc0,boot-partition-size=1048576,boot-config=8 This is a global change requiring more thinking. Nevertheless, in the case of the ast2600-evb machine booting from an eMMC device and when default devices are created, the proposed change still makes sense since the device is required to have boot areas. Cc: Jan Luebbe <jlu@pengutronix.de> Fixes: e554e45b4478 ("aspeed: Tune eMMC device properties to reflect HW strapping") Signed-off-by: Cédric Le Goater <clg@redhat.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Jan Luebbe <jlu@pengutronix.de> Acked-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04aspeed: Support create flash devices via command line for AST1030Jamin Lin1-10/+12
Add a "if-statement" in aspeed_minibmc_machine_init function. If users add "-nodefaults" in command line, the flash devices should be created by users setting. Otherwise, the flash devices are created at machine init. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/sd/aspeed_sdhci: Introduce Capabilities Register 2 for SD slot 0 and 1Jamin Lin1-11/+29
The size of SDHCI capabilities register is 64bits, so introduces new Capabilities Register 2 for SD slot 0 (0x144) and SD slot1 (0x244). Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> [ clg: Fixed code alignment ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/timer/aspeed: Fix interrupt status does not be cleared for AST2600Jamin Lin1-1/+1
According to the datasheet of AST2600 description, interrupt status set by HW and clear to "0" by software writing "1" on the specific bit. Therefore, if firmware set the specific bit "1" in the interrupt status register(0x34), the specific bit of "s->irq_sts" should be cleared 0. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Fixes: fadefada4d07 ("aspeed/timer: Add support for IRQ status register on the AST2600") Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/timer/aspeed: Fix coding styleJamin Lin1-5/+8
Fix coding style issues from checkpatch.pl Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04aspeed/soc: Support RTC for AST2700Jamin Lin1-0/+11
The RTC controller between AST2600 and AST2700 are identical. Add RTC model for AST2700 RTC support. The RTC controller registers base address is start at 0x12C0_F000 and its alarm interrupt is connected to GICINT13. Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/arm/aspeed_ast27x0: Avoid hardcoded '256' in IRQ calculationPeter Maydell1-4/+3
When calculating the index into the GIC's GPIO array for per-CPU interrupts, we have to start with the number of SPIs. The code currently hard-codes this to 'NUM_IRQS = 256'. However the number of SPIs is set separately and implicitly by the value of AST2700_MAX_IRQ, which is the number of SPIs plus 32 (since it is what we set the GIC num-irq property to). Define AST2700_MAX_IRQ as the total number of SPIs; this brings AST2700 into line with AST2600, which defines AST2600_MAX_IRQ as the number of SPIs not including the 32 internal interrupts. We can then use AST2700_MAX_IRQ instead of the hardcoded 256. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04hw/arm/aspeed_ast27x0: Use bsa.h for PPI definitionsPeter Maydell1-9/+10
Use the private peripheral interrupt definitions from bsa.h instead of defining them locally. Note that bsa.h defines these values as INTID values, which are all 16 greater than the PPI values that we were previously using. So we refactor the code to use INTID-based values to match that. This is the same thing we did in commit d40ab068c07d9 for sbsa-ref. It removes the "same constant, different values" confusion where this board code and bsa.h both define an ARCH_GIC_MAINT_IRQ, and allows us to use symbolic names for the timer interrupt IDs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04hw/sd/sdcard: Fix calculation of size when using eMMC boot partitionsJan Luebbe1-1/+3
The sd_bootpart_offset() function calculates the *runtime* offset which changes as the guest switches between accessing the main user data area and the boot partitions by writing to the EXT_CSD_PART_CONFIG_ACC_MASK bits, so it shouldn't be used to calculate the main user data area size. Instead, subtract the boot_part_size directly (twice, as there are two identical boot partitions defined by the eMMC spec). Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Jan Luebbe <jlu@pengutronix.de> Fixes: c8cb19876d3e ("hw/sd/sdcard: Support boot area in emmc image") Tested-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Cédric Le Goater <clg@redhat.com>
2024-11-04hw/arm: enable at24c with aspeedPatrick Leis1-0/+1
Enable AT24C with ASPEED in the KConfig because the boards build this device. Signed-off-by: Patrick Leis <venture@google.com> Reviewed-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2024-11-04MAINTAINERS: Remove myself as reviewerDavid Gibson1-2/+0
I've now well and truly moved on from ppc and qemu maintenance. I'm occupied with other things and am pretty much just ignoring mails on these topics I'm CCed on. Time to remove myself. I'm still listed as a reviewer for Device Tree, I'll keep this for now, since I do have some interest and it's lower volume. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04MAINTAINERS: Remove myself from XIVECédric Le Goater1-1/+0
Working on XIVE has been one of the most complex and fascinating experiences for me. It's been a real journey, and now it's time for IBM to take over and guide its future. I'm stepping back as the maintainer of XIVE. Cc: Michael Kowal <kowal@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04MAINTAINERS: Remove myself from the PowerNV machinesCédric Le Goater1-1/+0
It's been an amazing experience working on PowerNV systems all these years. Now it's time for IBM to take the lead on the QEMU machine and shape its future. I'm stepping back as the maintainer of PowerNV. Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04hw/ppc: Consolidate ppc440 initial mapping creation functionsBALATON Zoltan5-85/+28
Add a utility function and use it to replace very similar create_initial_mapping functions in 440 based machines. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04hw/ppc: Consolidate e500 initial mapping creation functionsBALATON Zoltan4-45/+33
Add booke206_set_tlb() utility function and use it to replace very similar create_initial_mapping functions in e500 machines. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04tests/qtest: Add XIVE tests for the powernv10 machineFrederic Barrat6-0/+853
These XIVE tests include: - General interrupt IRQ tests that: - enable and trigger an interrupt - acknowledge the interrupt - end of interrupt processing - Test the Pull Thread Context to Odd Thread Reporting Line - Test the different cache flush inject and queue sync inject operations Co-authored-by: Frederic Barrat <fbarrat@linux.ibm.com> Co-authored-by: Glenn Miles <milesg@linux.ibm.com> Co-authored-by: Michael Kowal <kowal@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Glenn Miles <milesg@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive2: TIMA CI ops using alternative offsets or byte lengthsMichael Kowal2-1/+12
Some of the TIMA Special CI operations perform the same operation at alternative byte offsets and lengths. The following xive2_tm_opertions[] table entries are missing when they exist for other offsets/sizes and have been added: - lwz@0x810 Pull/Invalidate O/S Context to register added lwz@0x818 exists ld @0x818 exists - lwz@0x820 Pull Pool Context to register added lwz@0x828 exists ld @0x828 exists - lwz@0x830 Pull Thread Context to register added lbz@0x838 exists Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive2: TIMA support for 8-byte OS context push for PHYPGlenn Miles2-5/+21
PHYP uses 8-byte writes to the 2nd doubleword of the OS context line when dispatching an OS level virtual processor. This support was not used by OPAL/Linux and so was never added. Without this support, the XIVE code doesn't notice that a new context is being pushed and fails to check for unpresented pending interrupts for that context. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive: Update PIPR when updating CPPRGlenn Miles1-2/+32
Current code was updating the PIPR inside the xive_tctx_accept() function instead of the xive_tctx_set_cppr function, which is where the HW would have it updated. Moved the update to the xive_tctx_set_cppr function which required additional support for pool interrupts. Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more privileged") Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive: Add special handling for pool targetsGlenn Miles1-10/+26
Hypervisor "pool" targets do not get their own interrupt line and instead must share an interrupt line with the hypervisor "physical" targets. This also means that the pool ring must use some of the registers from the physical ring in the TIMA. Specifically, the NSR, PIPR and CPPR registers: NSR = Notification Source Register PIPR = Post Interrupt Priority Register CPPR = Current Processor Priority Register The NSR specifies that there is an active interrupt. The CPPR specifies the priority of the context and the PIPR specifies the priority of the interrupt. For an interrupt to be presented to a context, the priority of the interrupt must be higher than the priority of the context it is interrupting (value must be lower). The existing code was not aware of the sharing of these registers. This commit adds that support. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Support "Pull Thread Context to Odd Thread Reporting Line"Glenn Miles5-32/+69
Adds support for single byte writes to offset 0xC38 of the TIMA address space. When this offset is written to, the hardware disables the thread context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the THREAD CAM entry. Note that this operation is almost identical to what we are already doing for the "Pull OS Context to Odd Thread Reporting Line" operation except that it also invalidates the Pool and Thread Contexts. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Change context/ring specific functions to be genericMichael Kowal3-14/+14
Some the functions that have been created are specific to a ring or context. Some of these same functions are being changed to operate on any ring/context. This will simplify the next patch sets that are adding additional ring/context operations. Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Support "Pull Thread Context to Register" operationGlenn Miles2-0/+17
Adds support for single byte read of offset 0x838 of the TIMA address space. According to the XIVE2 Specification, this causes the hardware to atomically: 1. Read the number of bytes requested (lbz or lhz are supported). 2. Reset the valid bit of the thread context. 3. Return the number of bytes requested in step 1 to a register. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Allow 1-byte write of Target field in TIMAGlenn Miles4-0/+18
When running PowerVM, the console is littered with XIVE traces regarding invalid writes to TIMA address 0x100b6 due to a lack of support for writes to the "TARGET" field which was added for XIVE GEN2. To fix this, we add special op support for 1-byte writes to this field. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Dump the VP-group and crowd tables with 'info pic'Frederic Barrat4-3/+114
The 'info pic' HMP command dumps the state of the interrupt controller. Add the dump of the NVG and NVC tables to its output to ease debug. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Dump more NVP state with 'info pic'Frederic Barrat2-2/+9
The 'PGoFirst' field of a Notify Virtual Processor tells if the NVP belongs to a VP group. Also, print the Reporting Cache Line address, if defined. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive2: Support for "OS LGS Push" TIMA operationGlenn Miles1-0/+15
Adds support for single byte writes to offset 0x15 of the TIMA address space. This offset holds the Logical Server Group Size (LGS) field. The field is used to evenly distribute the interrupt load among the members of a group, but is unused in the current implementation so we just support the writing of the value for now. Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive2: Support TIMA "Pull OS Context to Odd Thread Reporting Line"Frederic Barrat5-27/+142
Adds support for single byte writes to offset 0xC18 of the TIMA address space. When this offset is written to, the hardware disables the OS context and copies the current state information to the odd cache line of the pair specified by the NVT structure indexed by the OS CAM entry. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive2: Define OGEN field in the TIMAFrederic Barrat2-0/+5
The OGEN field at offset 0x1F is a new field for Gen2 TIMA. This patch defines it. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04pnv/xive: TIMA patch sets pre-req alignment and formatting changesMichael Kowal2-40/+64
Making some pre-requisite alignment changes ahead of the following patch sets. Making these changes now will ease the review of the patch sets. Checkpatch wants the closing comment '*/' on a separate line, unless it is on the same line as the starting comment '/*'. There are also changes to prevent lines from spanning 80 columns. Changed block of defines from: #define A 1 /* original define comment is not * preferred, but not flagged... */ #define B 2 /* Newly added define comment * is flagged with a warning */ To: #define A 1 /* original define comment is */ /* now fine, no warning... */ #define B 2 /* Newly added define comment */ /* is fine... */ Signed-off-by: Michael Kowal <kowal@linux.vnet.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/xive: Fix ESB length overflow on 32-bit hostsNicholas Piggin3-4/+4
The length of this region can be > 32-bits, which overflows size_t on 32-bit hosts. Change to uint64_t. Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04hw/ppc: Implement -dtb support for PowerNVAditya Gupta1-11/+40
Currently any device tree passed with -dtb option in QEMU, was ignored by the PowerNV code. Read and pass the passed -dtb to the kernel, thus enabling easier debugging with custom DTBs. The existing behaviour when -dtb is 'not' passed, is preserved as-is. But when a '-dtb' is passed, it completely overrides any dtb nodes or changes QEMU might have done, such as '-append' arguments to the kernel (which are mentioned in /chosen/bootargs in the dtb), hence add warning when -dtb is being used Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04spapr: nested: Add Power11 capability support for Nested PAPR guests in TCG L0Amit Machhiwal2-2/+15
The Power11 architected and raw mode support in Linux was merged via [1] and the corresponding support in QEMU is waiting to be added by [2] which in V6 currently. Add the Power11 capabilities and the required handling in TCG L0 implementation of the "Nested PAPR API". Note: This patch is based on [2]. [1] https://lore.kernel.org/all/20240221044623.1598642-1-mpe@ellerman.id.au/ [2] https://lore.kernel.org/all/20240731055022.696051-1-adityag@linux.ibm.com/ Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04spapr: nested: Add support for DPDES SPR in GSB for TCG L0Amit Machhiwal2-1/+3
The DPDES support for doorbell emulation and handling for KVM on PAPR guests was added in Linux via [1]. Subsequently, a new GSB (Guest State Buffer) element for DPDES was added in Linux; the same has been missing in TCG L0 implementation. Add support for DPDES register's APIv2 GSB element and required handling in `spapr_nested.c`. Currently, booting a KVM guest inside a QEMU TCG guest fails with the following crash. The crash occurs while handling the GUEST_RUN_VCPU hcall made in TCG L0. In the hcall handling path, map_and_getset_state() calls getset_state(), which, in turn, calls guest_state_request_check() to validate the GSR (Guest State Request) elements. During this process, guest_state_request_check() iterates over the GSR elements and receives a NULL return code from guest_state_element_type_find() for the type variable corresponding to the DPDES register's elemetn ID (which was unknown to TCG L0). Subsequently, getset_state() returns H_P3, ultimately leading to the hcall failure and causing the KVM guest to crash. KVM: unknown exit, hardware reason ffffffffffffffea [ ... KVM register dump ... ] Fix this by adding the required support in TCG L0 implementation of APIv2. [1] https://lore.kernel.org/all/20240605113913.83715-1-gautam@linux.ibm.com/ Fixes: 4a575f9a0567 ("spapr: nested: Initialize the GSB elements lookup table.") Suggested-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Amit Machhiwal <amachhiw@linux.ibm.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: reduce duplicate code between init_proc_POWER{9, 10}Harsh Prateek Bora1-46/+12
Historically, the registration of sprs have been inherited alongwith every new Power arch support being added leading to a lot of code duplication. It's time to do necessary cleanups now to avoid further duplication with newer arch support being added. Signed-off-by: Harsh Prateek Bora <harshb@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: combine multiple ail checks into oneHarsh Prateek Bora1-8/+2
ppc_excp_apply_ail has multiple if-checks for ail which is un-necessary. Combine them as appropriate. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: simplify var usage in ppc_next_unmasked_interruptHarsh Prateek Bora1-27/+27
As previously done for arch specific handlers, simplify var usage in ppc_next_unmasked_interrupt by caching the env->pending_interrupts and env->spr[SPR_LPCR] in local vars and using it later at multiple places. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: optimize p7 exception handling routinesHarsh Prateek Bora1-21/+25
Like p8 and p9, simplifying p7 exception handling rotuines to avoid un-necessary multiple indirect accesses to env->pending_interrupts and env->spr[SPR_LPCR]. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: optimize p8 exception handling routinesHarsh Prateek Bora1-28/+32
Most of the p8 exception handling accesses env->pending_interrupts and env->spr[SPR_LPCR] at multiple places. Passing it directly as local variables simplifies the code and avoids multiple indirect accesses. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: optimize p9 exception handling routinesHarsh Prateek Bora1-33/+39
Currently, p9 exception handling has multiple if-condition checks where it does an indirect access to pending_interrupts and LPCR via env. Pass the values during entry to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: optimize hreg_compute_pmu_hflags_valueHarsh Prateek Bora1-3/+3
The second if-condition can be true only if the first one above is true. Enclose the latter into the former to avoid un-necessary check if first condition fails. Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: optimize hreg_compute_pmu_hflags_valueHarsh Prateek Bora1-4/+5
Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple conditions to avoid multiple indirect accesses. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: use locally stored msr and avoid indirect accessHarsh Prateek Bora1-2/+2
hreg_compute_hflags_value already stores msr locally to be used in most of the logic in the routine however some instances are still using env->msr which is unnecessary. Use locally stored value as available. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04ppc/pseries: Add Power11 cpu typeAditya Gupta2-4/+14
Add sPAPR CPU Core definition for Power11 Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: Add Power11 DD2.0 processorAditya Gupta7-0/+86
Add CPU target code to add support for new Power11 Processor. Power11 core is same as Power10, hence reuse functions defined for Power10. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: Fix regression due to Power10 and Power11 having same PCRAditya Gupta1-0/+4
Power11 has the same PCR (Processor Compatibility Register) value, as Power10. Due to this, QEMU considers Power11 as a valid compat-mode for Power10, ie. earlier it was possible to run QEMU with '-M pseries,max-compat-mode=power11 --cpu power10' Same PCR also introduced a regression where `-M pseries --cpu power10` boots as Power11 (ie. logical PVR is of Power11, even though PVR is Power10). The regression was due to 'do_client_architecture_support' checking for valid compat modes and finding Power11 to be a valid compat mode for Power10 (it happens even without passing 'max-compat-mode' explicitly). Fix compat-mode issue and regression, by ensuring a future Power processor (with a higher logical_pvr value, eg. P11) cannot be valid compat-mode for an older Power processor (eg. P10) Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
2024-11-04target/ppc: Introduce 'PowerPCCPUClass::spapr_logical_pvr'Aditya Gupta2-0/+5
Introduce 'PnvChipClass::spapr_logical_pvr' to know corresponding logical PVR of a PowerPC CPU. This helps to have a one-to-one mapping between PVR and logical PVR for a CPU, and used in a later commit to handle cases where PCR of two generations of Power chip is same, which causes regressions with compat-mode. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Tested-by: Amit Machhiwal <amachhiw@linux.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
generated by cgit v1.1 at 2025-09-25 15:25:50 +0000