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2023-03-06hw/riscv/virt: Add a switch to disable ACPISunil V L2-0/+31
ACPI will be enabled by default. Add a switch to turn off for testing and debug purposes. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-3-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06hw/riscv/virt: Add OEM_ID and OEM_TABLE_ID fieldsSunil V L2-0/+7
ACPI needs OEM_ID and OEM_TABLE_ID for the machine. Add these fields in the RISCVVirtState structure and initialize with default values. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Message-ID: <20230302091212.999767-2-sunilvl@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Correctly set the device-tree entry 'mmu-type'Alexandre Ghiti1-8/+11
The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-6-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Introduce satp mode hw capabilitiesAlexandre Ghiti2-26/+75
Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230303131252.892893-5-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Allow user to set the satp modeAlexandre Ghiti3-7/+240
RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Ludovic Henry <ludovic@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-4-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Change type of valid_vm_1_10_[32|64] to boolAlexandre Ghiti1-10/+11
This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230303131252.892893-3-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-06riscv: Pass Object to register_cpu_props instead of DeviceStateAlexandre Ghiti1-14/+15
One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230303131252.892893-2-alexghiti@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05roms/opensbi: Upgrade from v1.1 to v1.2Bin Meng3-0/+0
Upgrade OpenSBI from v1.1 to v1.2 and the pre-built bios images. The v1.2 release includes the following commits: 994c8cf lib: sbi_timer: Added a conditional wait function which can timeout caa5eea lib: sbi: add check for ipi device for hsm start 0374ccf lib: sbi_hart: Shorten the code to set MPV bit 4e21cca lib: utils/serial: Update Shakti UART based on latest implementation 88b790f lib: sbi: Fix sbi_snprintf 1545afd lib: sbi: Fix counter index sanity check 83db3af lib: sbi: Add the bound check for events during config match 860a376 lib: sbi: Fix possible buffer overrun in counter validation 11c0008 lib: sbi: Fix fw_event_map initialization 8e86b23 lib: utils/fdt: Factor out common uart node code 7d28d3b lib: utils/serial: Initialize platform_uart_data to zero 7198e1d lib: serial: Clean up coding style in sifive-uart.c f272035 lib: utils/serial: Ensure baudrate is non-zero before using b9edf49 lib: sbi: Fix printf handling of long long 422f0e0 scripts: Add Kconfiglib v14.1.0 under scripts directory 662e631 Makefile: Add initial kconfig support for each platform de80e93 Makefile: Compile lib/utils sources separately for each platform 26bbff5 lib: utils/serial: Use kconfig for enabling/disabling drivers 2adc94b lib: utils/reset: Use kconfig for enabling/disabling drivers 3e76a60 lib: utils/sys: Use kconfig for enabling/disabling drivers 013dbb3 lib: utils/timer: Use kconfig for enabling/disabling drivers 76af9d4 lib: utils/ipi: Use kconfig for enabling/disabling drivers 0b1cf2f lib: utils/irqchip: Use kconfig for enabling/disabling drivers b126ce4 lib: utils/i2c: Use kconfig for enabling/disabling drivers 5616aa4 lib: utils/gpio: Use kconfig for enabling/disabling drivers 68d7b85 lib: utils/fdt: Use kconfig for enabling/disabling d514a8f platform: generic: Use kconfig for enabling/disabling overrides bc317a3 platform: generic: Use kconfig to set platform version and default name eccb9df platform: Remove redundant config.mk from all platforms 0723bab docs: Update documentation for kconfig support a6a8557 Makefile: Fix typo related to object.mk 9529e36 include: Add mstatus[h].GVA encodings 1fbe777 lib: sbi_trap: Save mstatus[h].GVA in trap->gva 1c4ce74 lib: sbi: Set gva when creating sbi_trap_info 5a0ca09 lib: sbi_trap: Set hypervisor CSRs for HS-mode a69eb6c lib: sbi_trap: Set hstatus.GVA when going to HS-mode 111afc1 lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop adf44b5 lib: sbi: Use the official extension name for AIA M-mode CSRs cbaa9b0 lib: utils: serial: Add Cadence UART driver 622cc5f include: Remove sideleg and sedeleg a90cf6b lib: sbi_pmu: Remove "event_idx" member from struct sbi_pmu_fw_event 1664d0e lib: sbi_pmu: Replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read() e238459 lib: sbi_pmu: Firmware counters are always 64 bits wide c9b388d lib: sbi_pmu: Simplify FW counters to reduce memory usage d10c1f4 lib: sbi_pmu: Add custom PMU device operations ee69f8e lib: sbi: Print platform PMU device at boot-time 5019fd1 include: sbi: Reduce includes in sbi_pmu.h d32b0a9 docs: pmu: fix Unmatched example typo 19664f6 docs: pmu: extend bindings example for Unmatched 37a0d83 lib: sbi_trap: Add helper to get GVA in sbi_trap_regs 46e744a lib: sbi_misaligned_ldst: Set GVA if not emulating 8ce486a lib: utils/fdt: Fix DT parsing in fdt_pmu_setup() 49372f2 lib: sbi: Fix sbi_strnlen wrong count decrement 7f09fba lib: utils/serial: add semihosting support 7105c18 docs/firmware: Update FW_JUMP documentation 3f3d401 docs: Fix some typos e54cb32 lib: sbi_pmu: move pmu irq information into pmu itself c316fa3 lib: sbi_hart: move hart_features struct to a public location 4f2acb5 lib: sbi_platform: expose hart_features to extension_init callback 2f63f24 platform: generic: add extensions_init handler and platform-override b6e520b platform: generic: allwinner: add support for c9xx pmu 98aa127 include: sbi: Fix typo in comment 11d14ae lib: sbi: Fix typo in comment 60b78fe include: sbi: Fix grammar in comment dcdaf30 lib: sbi: Add sbi_domain_root_add_memrange() API bd7ef41 platform: andes/ae350: Remove enabling cache from an350_final_init 9899b59 platform: andes/ae350: Use kconfig to set platform version and default name 88f58a3 platform: andes/ae350: Use fdt serial driver ef9f02e lib: utils/timer: Add Andes fdt timer support 8234fc1 lib: utils/reset: Add Andes fdt reset driver support 127a3f2 platform: andes/ae350: Use fdt irqchip driver 6f3258e platform: andes/ae350: Add fw_platform_init for platform initialization ce7c490 lib: utils/ipi: Add Andes fdt ipi driver support c8683c5 platform: andes/ae350: Add AE350 domain support d682a0a docs: andes-ae350.md: Update ae350 documentation for fdt driver support 0fee0bf Makefile: Add cscope support 51acd49 docs/firmware: update the document 9d54f43 Makefile: Add rules for carray sources in lib/sbi 56bed1a lib: sbi_ecall: Generate extensions list with carray 22f38ee lib: sbi_ecall: Add Kconfig option for each extension 85cf56c lib: utils/fdt: Remove redundant code 21ba418 lib: utils/fdt: Simplified code 8e9966c docs: fix some typos 7b29264 lib: utils/serial: Fix semihosting compile error using LLVM 14f5c4c lib: sbi_ecall: Split up sbi_ecall_replace 8e63716 firmware: payloads: Optimize usage of "ALIGN" 1b0d71b platform: generic/allwinner: Remove unused header files 9a740f5 platform: generic/allwinner: Remove ghostly type cast ba32021 Makefile: replace `echo` with `printf` for compatibility 49b0e35 Makefile: bugfix for handling platform paths 74e2029 lib: sbi: Simplified mmio match checking fc82e84 lib: sbi: Fix is_region_valid() f8eec91 lib: simplify fdt_parse_plmt_node() cc54184 lib: simplify fdt_parse_plicsw_node() e9bc7f1 lib: fix fdt_parse_plmt_node() 5daa0ef lib: fix fdt_parse_plicsw_node() 1f6866e lib: simplify fdt_translate_address() ad2ac29 lib: fix fdt_parse_aclint_node() cfbabb9 firmware: Minor optimization for relocate a36d455 platform: generic/andes: Enable generic platform support for AE350 6cd4b9b docs: platform: Update AE350 and generic platform documentation d3fcff7 docs: andes-ae350.md: fix watchdog nodename in dts example 4640d04 scripts/create-binary-archive.sh: remove andes/ae350 build directory e977512 lib: utils: Add fdt_fixup_node() helper function e1a0cb0 gitignore: add vim swap files ed8b8f5 platform: generic: Make use of fdt_match_node() 8b00be6 lib: fix is_region_valid() c2be214 lib: fix __fdt_parse_region() 7b08778 lib: fix irqchip_plic_update_hartid_table cb568b9 lib: sbi: Synchronize PMP settings with virtual memory system 506928a scripts: use env to invoke bash 64e8b9f lib: utils: serial: Add Renesas SCIF driver 0021b43 lib: utils: serial: Add FDT driver for Renesas SCIF 6840902 lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100 8b1617d platform: generic: Add Renesas RZ/Five initial support 7a3354a docs: platform: Add documentation for Renesas RZ/Five SoC 34da663 lib: utils/irqchip: plic: Fix the off-by-one error in priority save/restore helpers 8509e46 lib: utils/irqchip: plic: Ensure no out-of-bound access in priority save/restore helpers 91c8a7d lib: utils/irqchip: plic: Fix the off-by-one error in plic_context_init() fabbc00 lib: utils/irqchip: plic: Fix the off-by-one error in context save/restore helpers 9a2eeb4 lib: utils/irqchip: plic: Ensure no out-of-bound access in context save/restore helpers a8ee82c lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible ca7810a lib: utils/timer: mtimer: add a quirk for lacking mtime register b848d87 lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible 391ec85 docs: pmu: fix binding example 0412460 docs: pmu: update a reference to a deprecated property name d5d12a9 docs: pmu: Update the pmu doc with removal of mcountinhbit restriction 6b5188c include: Bump-up version to 1.2 Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: <20230207044003.3669059-1-bmeng@tinylab.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20230303202448.11911-3-palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05gitlab/opensbi: Move to docker:stablePalmer Dabbelt2-2/+3
The OpenSBI build has been using docker:19.03.1, which appears to be old enough that v2 of the manifest is no longer supported. Something has started serving us those manifests, resulting in errors along the lines of $ docker build --cache-from $IMAGE_TAG --tag $CI_REGISTRY_IMAGE:$CI_COMMIT_SHA --tag $IMAGE_TAG .gitlab-ci.d/opensbi Step 1/7 : FROM ubuntu:18.04 18.04: Pulling from library/ubuntu mediaType in manifest should be 'application/vnd.docker.distribution.manifest.v2+json' not 'application/vnd.oci.image.manifest.v1+json' This moves to docker:stable, as was suggested by the template. It also adds the python3 package via apt, as OpenSBI requires that to build. Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230303202448.11911-2-palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05hw: intc: Use cpu_by_arch_id to fetch CPU stateMayuresh Chitale3-13/+13
Qemu_get_cpu uses the logical CPU id assigned during init to fetch the CPU state. However APLIC, IMSIC and ACLINT contain registers and states which are specific to physical hart Ids. The hart Ids in any given system might be sparse and hence calls to qemu_get_cpu need to be replaced by cpu_by_arch_id which performs lookup based on the sparse physical hart IDs. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230303065055.915652-3-mchitale@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: cpu: Implement get_arch_id callbackMayuresh Chitale1-0/+8
Implement the callback for getting the architecture-dependent CPU ID ie mhartid. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230303065055.915652-2-mchitale@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05disas/riscv Fix ctzw disassembleIvan Klokov1-1/+1
Due to typo in opcode list, ctzw is disassembled as clzw instruction. Signed-off-by: Ivan Klokov <ivan.klokov@syntacore.com> Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230217151459.54649-1-ivan.klokov@syntacore.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05hw/riscv/virt.c: add cbo[mz]-block-size fdt propertiesAnup Patel1-0/+11
The cbom-block-size fdt property property is used to inform the OS about the blocksize in bytes for the Zicbom cache operations. Linux documents it in Documentation/devicetree/bindings/riscv/cpus.yaml as: riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicbom cache operations. cboz-block-size has the same role but for the Zicboz extension, i.e. informs the size in bytes for Zicboz cache operations. Linux support for it is under review/approval in [1]. Patch 3 of that series describes cboz-block-size as: riscv,cboz-block-size: $ref: /schemas/types.yaml#/definitions/uint32 description: The blocksize in bytes for the Zicboz cache operations. [1] https://lore.kernel.org/all/20230224162631.405473-1-ajones@ventanamicro.com/ Cc: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Bin Meng <bmeng@tinylab.org> Message-ID: <20230302091406.407824-2-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholderChristoph Muellner1-0/+1
The cmo.prefetch instructions are nops for QEMU (no emulation of the memory hierarchy, no illegal instructions, no permission faults, no traps). Add a comment noting where they would be decoded in case cbo.prefetch instructions become relevant in the future. Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-5-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: implement Zicbom extensionChristoph Muellner6-0/+106
Zicbom is the Cache-Block Management extension defined in the already ratified RISC-V Base Cache Management Operation (CBO) ISA extension [1]. The extension contains three instructions: cbo.clean, cbo.flush and cbo.inval. All of them must be implemented in the same group as LQ and cbo.zero due to overlapping patterns. All these instructions can throw a Illegal Instruction/Virtual Instruction exception, similar to the existing cbo.zero. The same check_zicbo_envcfg() is used to handle these exceptions. Aside from that, these instructions also need to handle page faults and guest page faults. This is done in a new check_zicbom_access() helper. As with Zicboz, the cache block size for Zicbom is also configurable. Note that the spec determines that Zicbo[mp] and Zicboz can have different cache sizes (Section 2.7 of [1]), so we also include a 'cbom_blocksize' to go along with the existing 'cboz_blocksize'. They are set to the same size, so unless users want to play around with the settings both sizes will be the same. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224132536.552293-4-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-05target/riscv: implement Zicboz extensionChristoph Muellner7-1/+117
The RISC-V base cache management operation (CBO) ISA extension has been ratified. It defines three extensions: Cache-Block Management, Cache-Block Prefetch and Cache-Block Zero. More information about the spec can be found at [1]. Let's start by implementing the Cache-Block Zero extension, Zicboz. It uses the cbo.zero instruction that, as with all CBO instructions that will be added later, needs to be implemented in an overlap group with the LQ instruction due to overlapping patterns. cbo.zero throws a Illegal Instruction/Virtual Instruction exception depending on CSR state. This is also the case for the remaining cbo instructions we're going to add next, so create a check_zicbo_envcfg() that will be used by all Zicbo[mz] instructions. [1] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.1.pdf Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Signed-off-by: Christoph Muellner <cmuellner@linux.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Message-ID: <20230224132536.552293-3-dbarboza@ventanamicro.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-03-04configure: Disable thread-safety warnings on macOSThomas Huth1-1/+4
The enablement of -Wthread-safety broke compilation on macOS (if -Werror is enabled, like in our CI). Disable it there by default until the problems are resolved. Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20230301113425.286946-1-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-04tests/qtest/migration-test: Disable migration/multifd/tcp/plain/cancelPeter Maydell1-2/+8
migration-test has been flaky for a long time, both in CI and otherwise: https://gitlab.com/qemu-project/qemu/-/jobs/3806090216 (a FreeBSD job) 32/648 ERROR:../tests/qtest/migration-helpers.c:205:wait_for_migration_status: assertion failed: (g_test_timer_elapsed() < MIGRATION_STATUS_WAIT_TIMEOUT) ERROR on a local macos x86 box: ▶ 34/621 ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed: assertion failed: (!g_str_equal(status, "failed")) ERROR 34/621 qemu:qtest+qtest-i386 / qtest-i386/migration-test ERROR 168.12s killed by signal 6 SIGABRT ――――――――――――――――――――――――――――――――――――― ✀ ――――――――――――――――――――――――――――――――――――― stderr: qemu-system-i386: Failed to peek at channel query-migrate shows failed migration: Unable to write to socket: Broken pipe ** ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed: assertion failed: (!g_str_equal(status, "failed")) (test program exited with status code -6) ―――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――――― ▶ 37/621 ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed: assertion failed: (!g_str_equal(status, "failed")) ERROR 37/621 qemu:qtest+qtest-x86_64 / qtest-x86_64/migration-test ERROR 174.37s killed by signal 6 SIGABRT ――――――――――――――――――――――――――――――――――――― ✀ ――――――――――――――――――――――――――――――――――――― stderr: query-migrate shows failed migration: Unable to write to socket: Broken pipe ** ERROR:../../tests/qtest/migration-helpers.c:151:migrate_query_not_failed: assertion failed: (!g_str_equal(status, "failed")) (test program exited with status code -6) In the cases where I've looked at the underlying log, this seems to be in the migration/multifd/tcp/plain/cancel subtest. Disable that specific subtest by default until somebody can track down the underlying cause. Enthusiasts can opt back in by setting QEMU_TEST_FLAKY_TESTS=1 in their environment. We might need to disable more parts of this test if this isn't sufficient to fix the flakiness. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Message-id: 20230302172211.4146376-1-peter.maydell@linaro.org
2023-03-04Merge tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu into stagingPeter Maydell6-71/+85
ppc patch queue for 2023-03-03: This queue includes a stub implementation for the dcblc instruction to avoid an illegal instrunction exception when using u-boot with mpc85xx. It also includes a PHB fix with user-created pnv-phb devices and Skiboot. # -----BEGIN PGP SIGNATURE----- # # iIwEABYKADQWIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCZAJllhYcZGFuaWVsaGI0 # MTNAZ21haWwuY29tAAoJEDzZypbeAzFk02YA/2YnJl0aRw6hgiayI2rLbcwQcVfp # oGAhh4QmqFL2UJw2AQDra0kh9sxBSEcqhltNnOa08tBnHPts3W/A8nmFtCd4Cw== # =VRNM # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 21:24:38 GMT # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: issuer "danielhb413@gmail.com" # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20230303' of https://gitlab.com/danielhb/qemu: pnv_phb4_pec: Simplify/align code to parent user-created PHBs pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful file pnv_phb4_pec: Only export existing PHBs to the device tree pnv_phb4_pec: Keep track of instantiated PHBs target/ppc/translate: Add dummy implementation for dcblc instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03pnv_phb4_pec: Simplify/align code to parent user-created PHBsFrederic Barrat5-25/+22
When instantiating a user-created PHB on P9/P10, we don't really have a reason any more to go through an indirection in pnv_chip_add_phb() in pnv.c, we can go straight to the right function in pnv_phb4_pec.c. That way, default PHBs and user-created PHBs are all handled in the same file. This patch also renames pnv_phb4_get_pec() to pnv_pec_add_phb() to better reflect that it "hooks" a PHB to a PEC. For P8, the PHBs are parented to the chip directly, so it makes sense to keep calling pnv_chip_add_phb() in pnv.c, to also be consistent with where default PHBs are handled. The only change here is that, since that function is now only used for P8, we can refine the return type. So overall, the PnvPHB front-end now has a pnv_phb_user_get_parent() function which handles the parenting of the user-created PHBs by calling the right function in the right file based on the processor version. It's also easily extensible if we ever need to support a different parent object. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-5-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Move pnv_phb4_get_pec() to rightful fileFrederic Barrat3-43/+42
The function pnv_phb4_get_pec() exposes some internals of the PEC and PHB logic, yet it was in the higher level hw/ppc/pnv.c file for historical reasons: P8 implements the PHBs from pnv.c directly, but on P9/P10, it's done through the CEC model, which has its own file. So move pnv_phb4_get_pec() to hw/pci-host/pnv_phb4_pec.c, where it fits naturally. While at it, replace the PnvPHB4 parameter by the PnvPHB front-end, since it has all the information needed and simplify it a bit. No functional changes. Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-4-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Only export existing PHBs to the device treeFrederic Barrat1-2/+6
So far, we were always exporting all possible PHBs to the device tree. It works well when using the default config but it potentially adds non-existing devices when using '-nodefaults' and user-created PHBs, causing the firmware (skiboot) to report errors when probing those PHBs. This patch only exports PHBs which have been realized to the device tree. Fixes: d786be3fe746 ("ppc/pnv: enable user created pnv-phb for powernv9") Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-3-fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03pnv_phb4_pec: Keep track of instantiated PHBsFrederic Barrat3-5/+10
Add an array on the PEC object to keep track of the PHBs which are instantiated. The array can be sparsely populated when using user-created PHBs. It will be useful for the next patch to only export instantiated PHBs in the device tree. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Message-Id: <20230302163715.129635-2-fbarrat@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03target/ppc/translate: Add dummy implementation for dcblc instructionBernhard Beschow1-0/+9
The dcblc instruction is used by u-boot in mpc85xx/start.S. Without it, an illegal istruction exception is generated very early in the boot process where the processor is not yet able to handle exceptions. See: https://github.com/u-boot/u-boot/blob/v2023.01/arch/powerpc/cpu/mpc85xx/start.S#L1840 Signed-off-by: Bernhard Beschow <shentey@gmail.com> Message-Id: <20230130184950.5241-1-shentey@gmail.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2023-03-03Merge tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu into ↵Peter Maydell16-77/+419
staging aspeed queue: * fix for the Aspeed I2C slave mode * a new I2C echo device from Klaus and its associated test in avocado. * initial SoC cleanups to allow the use of block devices instead of drives on the command line. * new facebook machines and eeprom fixes for the Fuji * readline fix # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmQAnrQACgkQUaNDx8/7 # 7KGIvQ//Te2eSxlZNxAXHb3HSVFRaBW+2EkJzNlalX75olFSzCLe8BnAHK5xPlYv # JjU0aPjWaPohPLdbNbAsJY2B8AwMGbUTjSv+ORRWF6s97LTVD9WcAYHgOTCz6d2X # ZrArJ5msEQAFEySOLmBqTcuyW3t4w8XeII+B09HZIS8Gn3F9kX5+4JCw9E4sX8fS # n9ayclMmrXCPbkGA4bfwJp3KI1Tc/WXNRyG0AmPEmepid7ECr5tVvQoXRMF1Sy/D # 10qbHEcmQXvZDy85M2ED1niOac4oU+EY8Wvjzkgc36uXcjqf0jIUfw56cwGSNVkW # MhPXSMiH4tEjgxmtzld3LeA6TGfrFcCvRXYiCuYWHjBS3gptlqY6Q0580vxoQVXL # lTYui57LB1YStNLcLG9toP0d4/fRfeqEx7ddCQKlopnW/K392eoJo0aYoVGVJhIC # 3QhN525EFUwMm4FDpdSW29Gfbk/ytpf0u4hQ6JPeBl8psirRKqCGuwr5NOnPYTaN # yErlsq2eL83t9kLo+2YIqgWic85wNP3kqAjIaE6lminqX7sWFH3V1g9HqUQZVG1g # msatZMiCCvwSFuz3DPkSfnuhqwaHuhvCATZloCtguCmnbUK9qUVVzvodKw62sZrd # GdS2XvRNyoOwezz0tDEvPipyZ7RpcaatryHNuzGwRsE5Lvr73dg= # =ExnJ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Mar 2023 13:03:48 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-aspeed-20230302' of https://github.com/legoater/qemu: aspeed/smc: Replace SysBus IRQs with GPIO lines aspeed: Add a boot_rom overlap region in the SoC spi_boot container aspeed: Introduce a spi_boot region under the SoC aspeed/fuji : correct the eeprom size hw/at24c : modify at24c to support 1 byte address mode hw/arm/aspeed: Adding new machine Tiogapass in QEMU hw/arm/aspeed: Adding new machine Yosemitev2 in QEMU tests/avocado/machine_aspeed.py: Add an I2C slave test hw/misc: add a toy i2c echo device hw/i2c: only schedule pending master when bus is idle readline: fix hmp completion issue Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu into ↵Peter Maydell8-73/+70
staging pull-loongarch-20230303 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZAFb5wAKCRBAov/yOSY+ # 35hmA/sHIGXU5zQV6p6DBILFGEE6x91sPtV8WKY3zujVY0hsfD4SF6bKTaKJYisZ # EztZZ5/EunQcu/vfgO46YtYysEWzrzGiinbZ5lAjxk6sdlBYlfcTQLAQEEW3zPbP # qB3SiiGmGQ0iYFHIlkyi1tCF5OEmqqQKrHYrNVk6cGBoJle2PA== # =giPH # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 02:31:03 GMT # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20230303' of https://gitlab.com/gaosong/qemu: hw/loongarch/virt: add system_powerdown hmp command support target/loongarch: Implement Chip Configuraiton Version Register(0x0000) docs/system/loongarch: update loongson3.rst and rename it to virt.rst loongarch: Add smbios command line option. hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'migration-20230302-pull-request' of ↵Peter Maydell2-3/+26
https://gitlab.com/juan.quintela/qemu into staging Migraiton Pull request Hi This pull requests include: - use-after-free in test-vmstate (eric) - fix exec migration in windows (berberian) Please apply. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEGJn/jt6/WMzuA0uC9IfvGFhy1yMFAmQAynUACgkQ9IfvGFhy # 1yMAKhAAyLAVSDvCh8uRvAZ4sHzZTmCuvMpGol8wromFta9Ub0vLqcK8F3neYERb # xsRmYxcfaGR0dcf4j8CNAdUjO3NJjiSlWFqFYizIWZNQ2Hotgfkizxifk7l1eRO5 # L4TvOcdS0oRAgwLvcE9SDjtRMYwCBey/opgQCAaWWVk/NLDEYKNOuPNSdrpPhMPL # LBBPNj1ATmKYPGxsdm3U8VwFu9VuevmQ9AxEhW4Euf9Ex0Ie+hxGjHZmzrJrbYUL # 3p2cyu/ShU3MxsKowgmFnDkL3zyihYPAKhb1YJ+csRLFJX/zKVJcH7ZVzJOSR3GQ # ZoksI1RciwBfbl1IVD+TgrZrZnFd5ltto3zxSrjLFFnB4lhtg5bUDwMG8/o5qx3d # YaJOaeTJbmqd+SRPxrqbLWWGpsXUJc1rEVcYh2rclyOxvwda1xJrl7/2N2ZeS6VD # GO7FhcaprpxvLF+WYmhuCIS3RbOC35/Hx11bgQL8da8lxPQsOfsPTkRpzeWa4exX # ET+fqvlQp8ApHDVF/VA8vD31brSv3moL6GmVnZeT/Fi5xa7Ntb3Mnn5DkDoXgSKo # DQjie+ZTRJ/E4VbY53FAeUh4M3OPf5NaZyzgx3K68XMZJ6THiLmwqDa/vO53Q0QP # kMNVYAA9FbBFIozDpa2l+fCNxaawKqVBK4yYoEBZcBLYjb+7540= # =fku0 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 02 Mar 2023 16:10:29 GMT # gpg: using RSA key 1899FF8EDEBF58CCEE034B82F487EF185872D723 # gpg: Good signature from "Juan Quintela <quintela@redhat.com>" [full] # gpg: aka "Juan Quintela <quintela@trasno.org>" [full] # Primary key fingerprint: 1899 FF8E DEBF 58CC EE03 4B82 F487 EF18 5872 D723 * tag 'migration-20230302-pull-request' of https://gitlab.com/juan.quintela/qemu: Fix exec migration on Windows (w32+w64). test-vmstate: fix bad GTree usage, use-after-free Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Peter Maydell61-396/+357
into staging virtio,pc,pci: features, cleanups, fixes vhost-user support without ioeventfd word replacements in vhost user spec shpc improvements cleanups, fixes all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmQBO8QPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpMUMH/3/FVp4qaF4CDwCHn7xWFRJpOREIhX/iWfUu # lGkwxnB7Lfyqdg7i4CAfgMf2emWKZchEE2DamfCo5bIX0IgRU3DWcOdR9ePvJ29J # cKwIYpxZcB4RYSoWL5OUakQLCT3JOu4XWaXeVjyHABjQhf3lGpwN4KmIOBGOy/N6 # 0YHOQScW2eW62wIOwhAEuYQceMt6KU32Uw3tLnMbJliiBf3a/hPctVNM9TFY9pcd # UYHGfBx/zD45owf1lTVEQFDg0eqPZKWW29g5haiOd5oAyXHHolzu+bt3bU7lH46b # f7iP12LqDudyrgoF5YWv3NJ4HaGm5V3kPqNqLLF/mjF7alxG+N8= # =hN3h # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 00:13:56 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (53 commits) tests/data/acpi/virt: drop (most) duplicate files. hw/cxl/mailbox: Use new UUID network order define for cel_uuid qemu/uuid: Add UUID static initializer qemu/bswap: Add const_le64() tests: acpi: Update q35/DSDT.cxl for removed duplicate UID hw/i386/acpi: Drop duplicate _UID entry for CXL root bridge tests/acpi: Allow update of q35/DSDT.cxl hw/cxl: Add CXL_CAPACITY_MULTIPLIER definition hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXL hw/pci-bridge/cxl_downstream: Fix type naming mismatch hw/mem/cxl_type3: Improve error handling in realize() MAINTAINERS: Add Fan Ni as Compute eXpress Link QEMU reviewer intel-iommu: send UNMAP notifications for domain or global inv desc smmu: switch to use memory_region_unmap_iommu_notifier_range() memory: introduce memory_region_unmap_iommu_notifier_range() intel-iommu: fail DEVIOTLB_UNMAP without dt mode intel-iommu: fail MAP notifier without caching mode memory: Optimize replay of guest mapping chardev/char-socket: set s->listener = NULL in char_socket_finalize hw/pci: Trace IRQ routing on PCI topology ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03Merge tag 'pull-riscv-to-apply-20230303' of ↵Peter Maydell20-574/+538
https://gitlab.com/palmer-dabbelt/qemu into staging Fifth RISC-V PR for QEMU 8.0 * Experimantal support for writable misa. * Support for Svadu extension. * Support for the Zicond extension. * Fixes to gdbstub, CSR accesses, dependencies between the various floating-point exceptions, and XTheadMemPair. * Many cleanups. # -----BEGIN PGP SIGNATURE----- # # iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmQBrrUTHHBhbG1lckBk # YWJiZWx0LmNvbQAKCRAuExnzX7sYicHrD/9dHBDOYNwyT/C2Q31NHMcEsVN6J0kW # 0sVyDb2/TUFoXmClMwS6jZYQQwWD7tjjB7BDcvPJ0QKLblDoZFX5JyxpQypIKWcs # It/E6mk7aG0epH1GoB/mbHFDbeCm4tbo7Vf6cQGpV/vGWBUaOS67c5nenUK7Tlqw # NTr9qak+9NYVswvMHZ0lUKtO12W1g/1EVkict2/90P2snWbPZ+foWomifGNljmhy # 5WtCNp27uBKF/uuD9xubLOxSEcqtZFTuKJy7U3azV4I0IKfd6Is83Kd0IwBOrTgT # MYkFdtQE1jgbkXYVZjft6ymLuqJrcLFYwD8C2zdNAXJLk1Y+MCtGafgW6f6SkT6B # FrNaSOqQ9xXiaNStF2FwYdmZ476zcY+eEg2rH1grTwCMewZ9r7m3+H8iat/tR0pt # 9scYAre1oaL33LB6DGZi3JkssNYyj42sutcNao2hQXRHcsh+vv1dLR+Di2mO6Ji5 # MNfvEgCrWWZjNVSwvhwCXdJPqqpyTbkRf8HJEp0gWvjk6VoF8sWidDw/8oMLj+wW # qZur7GNe+piJNvly85aFSL9J3SX7RyNeDzX/yK3b4k+g6I/ZziQaNgQtB9gYcm6w # mj3snCwRbEMEhdhPH0+Chm0Wb97knHJS14Vq9wCe2xh16o3HM5FspboLFkGZMjDV # tRDPFb7pitwdlA== # =FMkl # -----END PGP SIGNATURE----- # gpg: Signature made Fri 03 Mar 2023 08:24:21 GMT # gpg: using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 # Subkey fingerprint: 2B3C 3747 4468 43B2 4A94 3A7A 2E13 19F3 5FBB 1889 * tag 'pull-riscv-to-apply-20230303' of https://gitlab.com/palmer-dabbelt/qemu: (59 commits) target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig target/riscv/vector_helper.c: create vext_set_tail_elems_1s() target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers target/riscv/csr.c: simplify mctr() target/riscv/csr.c: use env_archcpu() in ctr() target/riscv: Export Svadu property target/riscv: Add *envcfg.HADE related check in address translation target/riscv: Add *envcfg.PBMTE related check in address translation target/riscv: Add csr support for svadu target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions hw/riscv: Move the dtb load bits outside of create_fdt() hw/riscv: Skip re-generating DT nodes for a given DTB target/riscv: Add support for Zicond extension RISC-V: XTheadMemPair: Remove register restrictions for store-pair target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages target/riscv: Group all predicate() routines together target/riscv: Drop priv level check in mseccfg predicate() target/riscv: Allow debugger to access sstc CSRs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-03-03hw/loongarch/virt: add system_powerdown hmp command supportSong Gao3-0/+14
For loongarch virt machine, add powerdown notification callback and send ACPI_POWER_DOWN_STATUS event by acpi ged. Also add acpi dsdt table for ACPI_POWER_BUTTON_DEVICE device in this patch. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230303010548.295580-1-gaosong@loongson.cn>
2023-03-03target/loongarch: Implement Chip Configuraiton Version Register(0x0000)Song Gao2-0/+3
According to the 3A5000 manual 4.1 implement Chip Configuration Version Register(0x0000). Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230227071046.1445572-1-gaosong@loongson.cn>
2023-03-03docs/system/loongarch: update loongson3.rst and rename it to virt.rstSong Gao1-59/+38
Since the EDK2 had already support LoongArch, update build bios, and update cpu type, cross-tools. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230227035905.1290953-1-gaosong@loongson.cn>
2023-03-03loongarch: Add smbios command line option.Song Gao1-1/+1
LoongArch has enabled CONFIG_SMBIOS, but didn't enable CLI '-smbios'. Fixes: 3efa6fa1e629 ("hw/loongarch: Add smbios support") Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230227035905.1290953-2-gaosong@loongson.cn>
2023-03-03hw/loongarch/virt: rename PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASEBibo Mao3-13/+14
In theory gsi base can start from 0 on loongarch virt machine, however gsi base is hard-coded in linux kernel loongarch system, else system fails to boot. This patch renames macro PCH_PIC_IRQ_OFFSET with VIRT_GSI_BASE, keeps value unchanged. GSI base is common concept in acpi spec and easy to understand. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20221228030719.991878-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-03-02tests/data/acpi/virt: drop (most) duplicate files.Michael S. Tsirkin14-0/+0
When virt ACPI files were added, lots of duplicates were created because we forgot that there's a no-prefix fallback: e.g. if tests/data/acpi/virt/APIC.memhp is not there then test will use tests/data/acpi/virt/APIC. Drop these. These were found with $find tests/data/acpi/ -type f -exec sha256sum '{}' ';'|sort -d|uniq -w 64 --all-repeated=separate (trick: -d does a dictionary sort so a no-suffix file ends up first). Note: there are still a bunch of issues with duplicates left even after this. First pc and q35 are often identical. Second, sometimes files are identical but not identical to the default fallback, e.g. tests/data/acpi/pc/SLIT.cphp and tests/data/acpi/pc/SLIT.memhp or tests/data/acpi/q35/HMAT.acpihmat-noinitiator and tests/data/acpi/virt/HMAT.acpihmatvirt Finding a way to deduplicate these is still a TODO item - softlinks maybe? We also need to make rebuild-expected-aml.sh smarter about not creating these duplicates in the 1st place. And maybe we should use softlinks instead of relying on a fallback to make it explicit what version does each test expect? Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/cxl/mailbox: Use new UUID network order define for cel_uuidIra Weiny3-9/+8
The cel_uuid was programatically generated previously because there was no static initializer for network order UUIDs. Use the new network order initializer for cel_uuid. Adjust cxl_initialize_mailbox() because it can't fail now. Update specification reference. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-11-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02qemu/uuid: Add UUID static initializerIra Weiny1-0/+12
UUID's are defined as network byte order fields. No static initializer was available for UUID's in their standard big endian format. Define a big endian initializer for UUIDs. Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-10-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02qemu/bswap: Add const_le64()Ira Weiny1-1/+11
Gcc requires constant versions of cpu_to_le* calls. Add a 64 bit version. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-9-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02tests: acpi: Update q35/DSDT.cxl for removed duplicate UIDJonathan Cameron2-1/+0
Dropping the ID effects this table in trivial fashion. Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-8-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/i386/acpi: Drop duplicate _UID entry for CXL root bridgeJonathan Cameron1-1/+0
Noticed as this prevents iASL disasembling the DSDT table. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-7-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02tests/acpi: Allow update of q35/DSDT.cxlJonathan Cameron1-0/+1
Next patch will drop duplicate _UID entry so allow update. Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-6-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/cxl: Add CXL_CAPACITY_MULTIPLIER definitionGregory Price1-6/+9
Remove usage of magic numbers when accessing capacity fields and replace with CXL_CAPACITY_MULTIPLIER, matching the kernel definition. Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-5-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/cxl: set cxl-type3 device type to PCI_CLASS_MEMORY_CXLGregory Price1-2/+1
Current code sets to STORAGE_EXPRESS and then overrides it. Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-4-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/pci-bridge/cxl_downstream: Fix type naming mismatchJonathan Cameron1-1/+1
Fix capitalization difference between struct name and typedef. Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-3-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02hw/mem/cxl_type3: Improve error handling in realize()Jonathan Cameron1-2/+10
msix_init_exclusive_bar() can fail, so if it does cleanup the address space. Reviewed-by: Ira Weiny <ira.weiny@intel.com> Reviewed-by: Gregory Price <gregory.price@memverge.com> Tested-by: Gregory Price <gregory.price@memverge.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230206172816.8201-2-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02MAINTAINERS: Add Fan Ni as Compute eXpress Link QEMU reviewerJonathan Cameron1-0/+1
Fan Ni has offered to help out with QEMU CXL emulation reviewing. Add him as a designated reviewer. Thanks to Fan for stepping up after I requested help following Ben stepping down as co-maintainer. Fan base been active in testing and review recently so great to have Fan on board. Based on patch [PATCH] MAINTAINERS: Remove CXL maintainer Ben Widawsky Message-id: <20230220212437.1462314-1-armbru@redhat.com> Message-Id: <20230228113926.11485-1-Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Markus Armbruster <armbru@redhat.com> Acked-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02intel-iommu: send UNMAP notifications for domain or global inv descPeter Xu1-5/+9
We don't send UNMAP notification upon domain or global invalidation which will lead the notifier can't work correctly. One example is to use vhost remote IOTLB without enabling device IOTLB. Fixing this by sending UNMAP notification. Signed-off-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-6-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02smmu: switch to use memory_region_unmap_iommu_notifier_range()Jason Wang1-15/+1
Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-5-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02memory: introduce memory_region_unmap_iommu_notifier_range()Jason Wang2-0/+23
This patch introduces a new helper to unmap the range of a specific IOMMU notifier. Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-4-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02intel-iommu: fail DEVIOTLB_UNMAP without dt modeJason Wang1-0/+8
Without dt mode, device IOTLB notifier won't work since guest won't send device IOTLB invalidation descriptor in this case. Let's fail early instead of misbehaving silently. Reviewed-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Laurent Vivier <lvivier@redhat.com> Tested-by: Viktor Prutyanov <viktor@daynix.com> Buglink: https://bugzilla.redhat.com/2156876 Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20230223065924.42503-3-jasowang@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2024-12-31 23:56:54 +0000