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2020-06-05hw/ssi/imx_spi: changed while statement to prevent underflowEden Mikitas1-1/+1
The while statement in question only checked if tx_burst is not 0. tx_burst is a signed int, which is assigned the value put by the guest driver in ECSPI_CONREG. The burst length can be anywhere between 1 and 4096, and since tx_burst is always decremented by 8 it could possibly underflow, causing an infinite loop. Signed-off-by: Eden Mikitas <e.mikitas@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-05target/s390x: Restrict system-mode declarationsPhilippe Mathieu-Daudé1-5/+7
As these declarations are restricted to !CONFIG_USER_ONLY in helper.c, only declare them when system-mode emulation is used. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200526172427.17460-8-f4bug@amsat.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05target/s390x/helper: Clean ifdef'ryPhilippe Mathieu-Daudé1-5/+0
All this code is guarded checking CONFIG_USER_ONLY definition. Drop the duplicated checks. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200526172427.17460-7-f4bug@amsat.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05target/s390x: Only compile decode_basedisp() on system-modePhilippe Mathieu-Daudé1-0/+4
The decode_basedisp*() methods are only used in ioinst.c, which is only build in system-mode emulation. I/O instructions are privileged, and other S instructions are decoded elsewhere. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Message-Id: <20200526172427.17460-6-f4bug@amsat.org> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05MAINTAINERS: add Thomas as additional s390x maintainerCornelia Huck1-0/+1
...because two people are better than one. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Acked-by: Thomas Huth <thuth@redhat.com> Cc: Thomas Huth <thuth@redhat.com> Message-Id: <20200525155855.225564-1-cohuck@redhat.com>
2020-06-05docs/s390x: document vfio-ccwCornelia Huck2-0/+78
Add a basic example for passing a dasd via vfio-ccw. Message-Id: <20200518075522.97643-1-cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05vfio-ccw: allow non-prefetch ORBsJared Rossi1-10/+3
Remove the explicit prefetch check when using vfio-ccw devices. This check does not trigger in practice as all Linux channel programs are intended to use prefetch. Newer Linux kernel versions do not require to force the PFCH flag with vfio-ccw devices anymore. Signed-off-by: Jared Rossi <jrossi@linux.ibm.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20200512181535.18630-2-jrossi@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05docs/s390x: document 3270Cornelia Huck2-0/+33
Add some basic info how to use 3270 devices. Message-Id: <20200515151518.83950-3-cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05docs/s390x: document the virtual cssCornelia Huck2-0/+87
Add some hints about "devno" rules. Message-Id: <20200515151518.83950-2-cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05s390x: pv: Fix KVM_PV_PREP_RESET command wrapper nameJanosch Frank3-4/+4
s390_pv_perf_clear_reset() is not a very helpful name since that function needs to be called for a normal and a clear reset via diag308. Let's instead name it s390_pv_prep_reset() which reflects the purpose of the function a bit better. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20200505124159.24099-1-frankja@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05s390x/kvm: help valgrind in several placesChristian Borntraeger1-2/+2
We need some little help in the code to reduce the valgrind noise. This patch does this with some designated initializers for the cpu model features and subfunctions. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20200429074201.100924-1-borntraeger@de.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2020-06-05Merge remote-tracking branch 'remotes/kraxel/tags/vga-20200605-pull-request' ↵Peter Maydell2-5/+11
into staging vga: ati security fix, cirrus cleanup. # gpg: Signature made Fri 05 Jun 2020 12:27:13 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20200605-pull-request: hw/display/cirrus_vga: Fix code mis-indentation ati-vga: check mm_index before recursive call (CVE-2020-13800) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-05Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell16-144/+134
staging Pull request # gpg: Signature made Fri 05 Jun 2020 10:47:27 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: block: Factor out bdrv_run_co() exec: Rename qemu_ram_writeback() as qemu_ram_msync() hw/block: Let the NVMe emulated device be target-agnostic memory: Extract memory_region_msync() from memory_region_writeback() memory: Rename memory_region_do_writeback -> memory_region_writeback fuzz: run the main-loop in fork-server process fuzz: add mangled object name to linker script fuzz: fix typo in i440fx-qtest-reboot arguments fuzz: add datadir for oss-fuzz compatability io_uring: use io_uring_cq_ready() to check for ready cqes io_uring: retry io_uring_submit() if it fails with errno=EINTR Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-05block: Factor out bdrv_run_co()Vladimir Sementsov-Ogievskiy1-121/+72
We have a few bdrv_*() functions that can either spawn a new coroutine and wait for it with BDRV_POLL_WHILE() or use a fastpath if they are alreeady running in a coroutine. All of them duplicate basically the same code. Factor the common code into a new function bdrv_run_co(). Signed-off-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-id: 20200520144901.16589-1-vsementsov@virtuozzo.com [Factor out bdrv_run_co_entry too] Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05exec: Rename qemu_ram_writeback() as qemu_ram_msync()Philippe Mathieu-Daudé3-4/+4
Rename qemu_ram_writeback() as qemu_ram_msync() to better match what it does. Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20200508062456.23344-5-philmd@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05hw/block: Let the NVMe emulated device be target-agnosticPhilippe Mathieu-Daudé2-5/+3
Now than the non-target specific memory_region_msync() function is available, use it to make this device target-agnostic. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20200508062456.23344-4-philmd@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05memory: Extract memory_region_msync() from memory_region_writeback()Philippe Mathieu-Daudé2-3/+20
Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20200508062456.23344-3-philmd@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05memory: Rename memory_region_do_writeback -> memory_region_writebackPhilippe Mathieu-Daudé3-4/+4
We usually use '_do_' for internal functions. Rename memory_region_do_writeback() as memory_region_writeback(). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 20200508062456.23344-2-philmd@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05fuzz: run the main-loop in fork-server processAlexander Bulekov3-0/+5
Without this, the time since the last main-loop keeps increasing, as the fuzzer runs. The forked children need to handle all the "past-due" timers, slowing them down, over time. With this change, the parent/fork-server process runs the main-loop, while waiting on the child, ensuring that the timer events do not pile up, over time. Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-id: 20200512030133.29896-5-alxndr@bu.edu Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05fuzz: add mangled object name to linker scriptAlexander Bulekov1-0/+5
Previously, we relied on "FuzzerTracePC*(.bss*)" to place libfuzzer's fuzzer::TPC object into our contiguous shared-memory region. This does not work for some libfuzzer builds, so this addition identifies the region by its mangled name: *(.bss._ZN6fuzzer3TPCE); Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-id: 20200512030133.29896-4-alxndr@bu.edu Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05fuzz: fix typo in i440fx-qtest-reboot argumentsAlexander Bulekov1-1/+1
Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20200512030133.29896-3-alxndr@bu.edu Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05fuzz: add datadir for oss-fuzz compatabilityAlexander Bulekov3-1/+18
This allows us to keep pc-bios in executable_dir/pc-bios, rather than executable_dir/../pc-bios, which is incompatible with oss-fuzz' file structure. Signed-off-by: Alexander Bulekov <alxndr@bu.edu> Reviewed-by: Darren Kenny <darren.kenny@oracle.com> Message-id: 20200512030133.29896-2-alxndr@bu.edu Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05io_uring: use io_uring_cq_ready() to check for ready cqesStefano Garzarella1-6/+3
In qemu_luring_poll_cb() we are not using the cqe peeked from the CQ ring. We are using io_uring_peek_cqe() only to see if there are cqes ready, so we can replace it with io_uring_cq_ready(). Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-id: 20200519134942.118178-1-sgarzare@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05io_uring: retry io_uring_submit() if it fails with errno=EINTRStefano Garzarella1-1/+1
As recently documented [1], io_uring_enter(2) syscall can return an error (errno=EINTR) if the operation was interrupted by a delivery of a signal before it could complete. This should happen when IORING_ENTER_GETEVENTS flag is used, for example during io_uring_submit_and_wait() or during io_uring_submit() when IORING_SETUP_IOPOLL is enabled. We shouldn't have this problem for now, but it's better to prevent it. [1] https://github.com/axboe/liburing/commit/344355ec6619de8f4e64584c9736530b5346e4f4 Signed-off-by: Stefano Garzarella <sgarzare@redhat.com> Message-id: 20200519133041.112138-1-sgarzare@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2020-06-05hw/display/cirrus_vga: Fix code mis-indentationPhilippe Mathieu-Daudé1-3/+3
While replacing fprintf() by qemu_log_mask() in commit 2b55f4d3504, we incorrectly used a 'tab = 4 spaces' alignment, leading to misindented new code. Fix now. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20200529165436.23573-1-f4bug@amsat.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2020-06-05ati-vga: check mm_index before recursive call (CVE-2020-13800)Prasad J Pandit1-2/+8
While accessing VGA registers via ati_mm_read/write routines, a guest may set 's->regs.mm_index' such that it leads to infinite recursion. Check mm_index value to avoid such recursion. Log an error message for wrong values. Reported-by: Ren Ding <rding@gatech.edu> Reported-by: Hanqing Zhao <hanqing@gatech.edu> Reported-by: Yi Ren <c4tren@gmail.com> Message-id: 20200604090830.33885-1-ppandit@redhat.com Suggested-by: BALATON Zoltan <balaton@eik.bme.hu> Suggested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2020-06-04Merge remote-tracking branch ↵Peter Maydell24-573/+480
'remotes/alistair/tags/pull-riscv-to-apply-20200603' into staging This is a collection of RISC-V patches for 5.1. This incldues removing deprecated features and part of the OpenTitan support series. # gpg: Signature made Wed 03 Jun 2020 17:12:43 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200603: riscv: Initial commit of OpenTitan machine target/riscv: Add the lowRISC Ibex CPU target/riscv: Don't set PMP feature in the cpu init target/riscv: Disable the MMU correctly target/riscv: Don't overwrite the reset vector riscv/boot: Add a missing header include riscv: sifive_e: Manually define the machine docs: deprecated: Update the -bios documentation target/riscv: Drop support for ISA spec version 1.09.1 target/riscv: Remove the deprecated CPUs hw/riscv: spike: Remove deprecated ISA specific machines hw/riscv: virt: Remove the riscv_ prefix of the machine* functions hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions riscv: Change the default behavior if no -bios option is specified riscv: Suppress the error report for QEMU testing with riscv_find_firmware() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-03riscv: Initial commit of OpenTitan machineAlistair Francis7-1/+278
This adds a barebone OpenTitan machine to QEMU. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03target/riscv: Add the lowRISC Ibex CPUAlistair Francis2-0/+11
Ibex is a small and efficient, 32-bit, in-order RISC-V core with a 2-stage pipeline that implements the RV32IMC instruction set architecture. For more details on lowRISC see here: https://github.com/lowRISC/ibex Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
2020-06-03target/riscv: Don't set PMP feature in the cpu initAlistair Francis1-5/+0
The PMP is enabled by default via the "pmp" property so there is no need for us to set it in the init function. As all CPUs have PMP support just remove the set_feature() call in the CPU init functions. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03target/riscv: Disable the MMU correctlyAlistair Francis1-2/+3
Previously if we didn't enable the MMU it would be enabled in the realize() function anyway. Let's ensure that if we don't want the MMU we disable it. We also don't need to enable the MMU as it will be enabled in realize() by default. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03target/riscv: Don't overwrite the reset vectorAlistair Francis1-1/+2
The reset vector is set in the init function don't set it again in realize. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03riscv/boot: Add a missing header includeAlistair Francis1-0/+1
As the functions declared in this header use the symbol_fn_t typedef itself declared in "hw/loader.h", we need to include it here to make the header file self-contained. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03riscv: sifive_e: Manually define the machineAlistair Francis2-11/+34
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-06-03docs: deprecated: Update the -bios documentationAlistair Francis1-15/+13
Update the -bios deprecation documentation to describe the new behaviour. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03target/riscv: Drop support for ISA spec version 1.09.1Alistair Francis8-210/+73
The RISC-V ISA spec version 1.09.1 has been deprecated in QEMU since 4.1. It's not commonly used so let's remove support for it. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03target/riscv: Remove the deprecated CPUsAlistair Francis4-52/+20
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-06-03hw/riscv: spike: Remove deprecated ISA specific machinesAlistair Francis3-228/+12
The ISA specific Spike machines have been deprecated in QEMU since 4.1, let's finally remove them. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
2020-06-03hw/riscv: virt: Remove the riscv_ prefix of the machine* functionsBin Meng1-10/+10
Remove the riscv_ prefix of the machine* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1590072147-13035-2-git-send-email-bmeng.cn@gmail.com Message-Id: <1590072147-13035-2-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-03hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functionsBin Meng1-12/+12
To keep consistency with the machine* functions, remove the riscv_ prefix of the soc* functions. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1590072147-13035-1-git-send-email-bmeng.cn@gmail.com Message-Id: <1590072147-13035-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-03riscv: Change the default behavior if no -bios option is specifiedBin Meng1-27/+4
Per QEMU deprecated doc, QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the virt machine and sifive_u machine. The default behavior has been that QEMU does not automatically load any firmware if no -bios option is included. Now 2 releases passed, it's time to change the default behavior to load the default OpenSBI firmware automatically. The firmware is included with the QEMU release and no user interaction is required. All a user needs to do is specify the kernel they want to boot with the -kernel option. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1588335545-649-1-git-send-email-bmeng.cn@gmail.com Message-Id: <1588335545-649-1-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-03riscv: Suppress the error report for QEMU testing with riscv_find_firmware()Bin Meng1-3/+11
We only ship plain binary bios images in the QEMU source. With Spike machine that uses ELF images as the default bios, running QEMU test will complain hence let's suppress the error report for QEMU testing. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> Message-Id: <1588348254-7241-6-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2020-06-02Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200602' into stagingPeter Maydell26-193/+736
Vector rotate support Signal handling support for NetBSD arm/aarch64 # gpg: Signature made Tue 02 Jun 2020 17:43:05 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20200602: accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handler accel/tcg: Adjust cpu_signal_handler for NetBSD/arm tcg: Improve move ops in liveness_pass_2 target/s390x: Use tcg_gen_gvec_rotl{i,s,v} target/ppc: Use tcg_gen_gvec_rotlv tcg/ppc: Implement INDEX_op_rot[lr]v_vec tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec tcg/i386: Implement INDEX_op_rotl{i,s,v}_vec tcg: Implement gvec support for rotate by scalar tcg: Remove expansion to shift by vector from do_shifts tcg: Implement gvec support for rotate by vector tcg: Implement gvec support for rotate by immediate Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2020-06-02accel/tcg: Provide a NetBSD specific aarch64 cpu_signal_handlerNick Hudson1-0/+27
Fix qemu build on NetBSD/evbarm-aarch64 by providing a NetBSD specific cpu_signal_handler. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20200517101529.5367-1-skrll@netbsd.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02accel/tcg: Adjust cpu_signal_handler for NetBSD/armNick Hudson1-3/+13
Fix building on NetBSD/arm by extracting the FSR value from the correct siginfo_t field. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-Id: <20200516154147.24842-1-skrll@netbsd.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02tcg: Improve move ops in liveness_pass_2Richard Henderson1-22/+56
If the output of the move is dead, then the last use is in the store. If we propagate the input to the store, then we can remove the move opcode entirely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02target/s390x: Use tcg_gen_gvec_rotl{i,s,v}Richard Henderson4-94/+11
Merge VERLL and VERLLV into op_vesv and op_ves, alongside all of the other vector shift operations. Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02target/ppc: Use tcg_gen_gvec_rotlvRichard Henderson3-25/+4
Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02tcg/ppc: Implement INDEX_op_rot[lr]v_vecRichard Henderson3-6/+20
We already had support for rotlv, using a target-specific opcode; convert to use the generic opcode. Handle rotrv via simple negation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2020-06-02tcg/aarch64: Implement INDEX_op_rotl{i,v}_vecRichard Henderson2-2/+52
For immediate rotate , we can implement this in two instructions, using SLI. For variable rotate, the oddness of aarch64 right-shift- as-negative-left-shift means a backend-specific expansion works best. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2024-11-03 16:51:45 +0000