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authorAlistair Francis <alistair.francis@wdc.com>2020-05-05 13:07:24 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-06-03 09:11:51 -0700
commit26cd0362dd43a32fc9a917f5c00b20e9dafa93be (patch)
treea32b850a57bfebf24bd3f68d4729b32d0fcc98db
parentb2a3a071f76d45c7ac2b8a1640153d3cc8259ca3 (diff)
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hw/riscv: spike: Remove deprecated ISA specific machines
The ISA specific Spike machines have been deprecated in QEMU since 4.1, let's finally remove them. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Thomas Huth <thuth@redhat.com>
-rw-r--r--docs/system/deprecated.rst17
-rw-r--r--hw/riscv/spike.c217
-rw-r--r--include/hw/riscv/spike.h6
3 files changed, 12 insertions, 228 deletions
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
index f0061f9..50927ba 100644
--- a/docs/system/deprecated.rst
+++ b/docs/system/deprecated.rst
@@ -379,13 +379,6 @@ This machine has been renamed ``fuloong2e``.
These machine types are very old and likely can not be used for live migration
from old QEMU versions anymore. A newer machine type should be used instead.
-``spike_v1.9.1`` and ``spike_v1.10`` (since 4.1)
-''''''''''''''''''''''''''''''''''''''''''''''''
-
-The version specific Spike machines have been deprecated in favour of the
-generic ``spike`` machine. If you need to specify an older version of the RISC-V
-spec you can use the ``-cpu rv64gcsu,priv_spec=v1.9.1`` command line argument.
-
Device options
--------------
@@ -493,6 +486,16 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0
The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and
'hostfwd_remove' HMP commands has been replaced by ``netdev_id``.
+System emulator machines
+------------------------
+
+``spike_v1.9.1`` and ``spike_v1.10`` (removed in 5.1)
+'''''''''''''''''''''''''''''''''''''''''''''''''''''
+
+The version specific Spike machines have been removed in favour of the
+generic ``spike`` machine. If you need to specify an older version of the RISC-V
+spec you can use the ``-cpu rv64gcsu,priv_spec=v1.10.0`` command line argument.
+
Related binaries
----------------
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index d0c4843..7bbbdb5 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -257,221 +257,6 @@ static void spike_board_init(MachineState *machine)
false);
}
-static void spike_v1_10_0_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.10.0 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* create device tree */
- create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */
- 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */
- 0xf1402573, /* csrr a0, mhartid */
-#if defined(TARGET_RISCV32)
- 0x0182a283, /* lw t0, 24(t0) */
-#elif defined(TARGET_RISCV64)
- 0x0182b283, /* ld t0, 24(t0) */
-#endif
- 0x00028067, /* jr t0 */
- 0x00000000,
- memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */
- 0x00000000,
- /* dtb: */
- };
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the device tree */
- if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) >
- memmap[SPIKE_MROM].size - sizeof(reset_vec)) {
- error_report("not enough space to store device-tree");
- exit(1);
- }
- qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt));
- rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt),
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-}
-
-static void spike_v1_09_1_board_init(MachineState *machine)
-{
- const struct MemmapEntry *memmap = spike_memmap;
-
- SpikeState *s = g_new0(SpikeState, 1);
- MemoryRegion *system_memory = get_system_memory();
- MemoryRegion *main_mem = g_new(MemoryRegion, 1);
- MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
- int i;
- unsigned int smp_cpus = machine->smp.cpus;
-
- if (!qtest_enabled()) {
- info_report("The Spike v1.09.1 machine has been deprecated. "
- "Please use the generic spike machine and specify the ISA "
- "versions using -cpu.");
- }
-
- /* Initialize SOC */
- object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
- TYPE_RISCV_HART_ARRAY, &error_abort, NULL);
- object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type",
- &error_abort);
- object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts",
- &error_abort);
- object_property_set_bool(OBJECT(&s->soc), true, "realized",
- &error_abort);
-
- /* register system main memory (actual RAM) */
- memory_region_init_ram(main_mem, NULL, "riscv.spike.ram",
- machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base,
- main_mem);
-
- /* boot rom */
- memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom",
- memmap[SPIKE_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base,
- mask_rom);
-
- if (machine->kernel_filename) {
- riscv_load_kernel(machine->kernel_filename, htif_symbol_callback);
- }
-
- /* reset vector */
- uint32_t reset_vec[8] = {
- 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */
- 0x00028067, /* jump to DRAM_BASE */
- 0x00000000, /* reserved */
- memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */
- 0, 0, 0, 0 /* trap vector */
- };
-
- /* part one of config string - before memory size specified */
- const char *config_string_tmpl =
- "platform {\n"
- " vendor ucb;\n"
- " arch spike;\n"
- "};\n"
- "rtc {\n"
- " addr 0x%" PRIx64 "x;\n"
- "};\n"
- "ram {\n"
- " 0 {\n"
- " addr 0x%" PRIx64 "x;\n"
- " size 0x%" PRIx64 "x;\n"
- " };\n"
- "};\n"
- "core {\n"
- " 0" " {\n"
- " " "0 {\n"
- " isa %s;\n"
- " timecmp 0x%" PRIx64 "x;\n"
- " ipi 0x%" PRIx64 "x;\n"
- " };\n"
- " };\n"
- "};\n";
-
- /* build config string with supplied memory size */
- char *isa = riscv_isa_string(&s->soc.harts[0]);
- char *config_string = g_strdup_printf(config_string_tmpl,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE,
- (uint64_t)memmap[SPIKE_DRAM].base,
- (uint64_t)ram_size, isa,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE,
- (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE);
- g_free(isa);
- size_t config_string_len = strlen(config_string);
-
- /* copy in the reset vector in little_endian byte order */
- for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
- reset_vec[i] = cpu_to_le32(reset_vec[i]);
- }
- rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SPIKE_MROM].base, &address_space_memory);
-
- /* copy in the config string */
- rom_add_blob_fixed_as("mrom.reset", config_string, config_string_len,
- memmap[SPIKE_MROM].base + sizeof(reset_vec),
- &address_space_memory);
-
- /* initialize HTIF using symbols found in load_kernel */
- htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0));
-
- /* Core Local Interruptor (timer and IPI) */
- sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
- false);
-
- g_free(config_string);
-}
-
-static void spike_v1_09_1_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)";
- mc->init = spike_v1_09_1_board_init;
- mc->max_cpus = 1;
-}
-
-static void spike_v1_10_0_machine_init(MachineClass *mc)
-{
- mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)";
- mc->init = spike_v1_10_0_board_init;
- mc->max_cpus = 1;
-}
-
static void spike_machine_init(MachineClass *mc)
{
mc->desc = "RISC-V Spike Board";
@@ -481,6 +266,4 @@ static void spike_machine_init(MachineClass *mc)
mc->default_cpu_type = SPIKE_V1_10_0_CPU;
}
-DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init)
-DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init)
DEFINE_MACHINE("spike", spike_machine_init)
diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
index dc77042..1cd72b8 100644
--- a/include/hw/riscv/spike.h
+++ b/include/hw/riscv/spike.h
@@ -39,11 +39,9 @@ enum {
};
#if defined(TARGET_RISCV32)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE32
#elif defined(TARGET_RISCV64)
-#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1
-#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
+#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_BASE64
#endif
#endif