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-rw-r--r--target/xtensa/cpu-param.h3
-rw-r--r--target/xtensa/cpu.c10
-rw-r--r--target/xtensa/cpu.h4
-rw-r--r--target/xtensa/dbg_helper.c3
-rw-r--r--target/xtensa/helper.c5
-rw-r--r--target/xtensa/mmu_helper.c3
-rw-r--r--target/xtensa/op_helper.c1
-rw-r--r--target/xtensa/translate.c35
-rw-r--r--target/xtensa/xtensa-semi.c1
9 files changed, 37 insertions, 28 deletions
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 5e4848a..7a0c22c 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,7 +16,6 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-/* Xtensa processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
+#define TARGET_INSN_START_EXTRA_WORDS 0
#endif
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 7663b62..27d6e40 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -36,7 +36,7 @@
#include "migration/vmstate.h"
#include "hw/qdev-clock.h"
#ifndef CONFIG_USER_ONLY
-#include "exec/memory.h"
+#include "system/memory.h"
#endif
@@ -232,10 +232,15 @@ static const struct SysemuCPUOps xtensa_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps xtensa_tcg_ops = {
+ /* Xtensa processors have a weak memory model */
+ .guest_default_memory_order = 0,
+ .mttcg_supported = true,
+
.initialize = xtensa_translate_init,
.translate_code = xtensa_translate_code,
.debug_excp_handler = xtensa_breakpoint_handler,
.restore_state_to_opc = xtensa_restore_state_to_opc,
+ .mmu_index = xtensa_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = xtensa_cpu_tlb_fill,
@@ -248,7 +253,7 @@ static const TCGCPUOps xtensa_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
+static void xtensa_cpu_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
@@ -262,7 +267,6 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
&xcc->parent_phases);
cc->class_by_name = xtensa_cpu_class_by_name;
- cc->mmu_index = xtensa_cpu_mmu_index;
cc->dump_state = xtensa_cpu_dump_state;
cc->set_pc = xtensa_cpu_set_pc;
cc->get_pc = xtensa_cpu_get_pc;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 8d70bfc..c03ed71 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -30,7 +30,9 @@
#include "cpu-qom.h"
#include "qemu/cpu-float.h"
+#include "exec/cpu-common.h"
#include "exec/cpu-defs.h"
+#include "exec/cpu-interrupt.h"
#include "hw/clock.h"
#include "xtensa-isa.h"
@@ -731,8 +733,6 @@ static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
#define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000
#define XTENSA_CSBASE_LBEG_OFF_SHIFT 16
-#include "exec/cpu-all.h"
-
static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c
index 5546c82..c4f4298 100644
--- a/target/xtensa/dbg_helper.c
+++ b/target/xtensa/dbg_helper.c
@@ -31,7 +31,8 @@
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
-#include "exec/address-spaces.h"
+#include "exec/watchpoint.h"
+#include "system/address-spaces.h"
void HELPER(wsr_ibreakenable)(CPUXtensaState *env, uint32_t v)
{
diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c
index 4824b97..2d93b45 100644
--- a/target/xtensa/helper.c
+++ b/target/xtensa/helper.c
@@ -29,6 +29,7 @@
#include "qemu/log.h"
#include "cpu.h"
#include "exec/cputlb.h"
+#include "exec/target_page.h"
#include "gdbstub/helpers.h"
#include "exec/helper-proto.h"
#include "qemu/error-report.h"
@@ -169,7 +170,7 @@ static void xtensa_finalize_config(XtensaConfig *config)
}
}
-static void xtensa_core_class_init(ObjectClass *oc, void *data)
+static void xtensa_core_class_init(ObjectClass *oc, const void *data)
{
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(oc);
@@ -191,7 +192,7 @@ void xtensa_register_core(XtensaConfigList *node)
TypeInfo type = {
.parent = TYPE_XTENSA_CPU,
.class_init = xtensa_core_class_init,
- .class_data = (void *)node->config,
+ .class_data = node->config,
};
xtensa_finalize_config(node->config);
diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c
index 63be741..a7dd810 100644
--- a/target/xtensa/mmu_helper.c
+++ b/target/xtensa/mmu_helper.c
@@ -33,8 +33,11 @@
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
#include "exec/cputlb.h"
+#include "accel/tcg/cpu-mmu-index.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
+#include "exec/target_page.h"
+#include "system/memory.h"
#define XTENSA_MPU_SEGMENT_MASK 0x0000001f
#define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index 028d4e0..c125fa4 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -31,6 +31,7 @@
#include "exec/page-protection.h"
#include "qemu/host-utils.h"
#include "exec/exec-all.h"
+#include "system/memory.h"
#include "qemu/atomic.h"
#include "qemu/timer.h"
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 4f02cef..2af83c0 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -35,14 +35,15 @@
#include "tcg/tcg-op.h"
#include "qemu/log.h"
#include "qemu/qemu-print.h"
-#include "semihosting/semihost.h"
#include "exec/translator.h"
#include "exec/translation-block.h"
-
+#include "exec/target_page.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
-
#include "exec/log.h"
+#ifndef CONFIG_USER_ONLY
+#include "semihosting/semihost.h"
+#endif
#define HELPER_H "helper.h"
#include "exec/helper-info.c.inc"
@@ -1394,11 +1395,11 @@ static void translate_bbi(DisasContext *dc, const OpcodeArg arg[],
const uint32_t par[])
{
TCGv_i32 tmp = tcg_temp_new_i32();
-#if TARGET_BIG_ENDIAN
- tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
-#else
- tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
-#endif
+ if (TARGET_BIG_ENDIAN) {
+ tcg_gen_andi_i32(tmp, arg[0].in, 0x80000000u >> arg[1].imm);
+ } else {
+ tcg_gen_andi_i32(tmp, arg[0].in, 0x00000001u << arg[1].imm);
+ }
gen_brcondi(dc, par[0], tmp, 0, arg[2].imm);
}
@@ -2241,17 +2242,15 @@ static uint32_t test_exceptions_simcall(DisasContext *dc,
const OpcodeArg arg[],
const uint32_t par[])
{
- bool is_semi = semihosting_enabled(dc->cring != 0);
-#ifdef CONFIG_USER_ONLY
- bool ill = true;
-#else
- /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
- bool ill = dc->config->hw_version <= 250002 && !is_semi;
-#endif
- if (ill || !is_semi) {
- qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
+#ifndef CONFIG_USER_ONLY
+ if (semihosting_enabled(dc->cring != 0)) {
+ return 0;
}
- return ill ? XTENSA_OP_ILL : 0;
+#endif
+ qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
+
+ /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
+ return dc->config->hw_version <= 250002 ? XTENSA_OP_ILL : 0;
}
static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
diff --git a/target/xtensa/xtensa-semi.c b/target/xtensa/xtensa-semi.c
index 2ded8e5..636f421 100644
--- a/target/xtensa/xtensa-semi.c
+++ b/target/xtensa/xtensa-semi.c
@@ -29,6 +29,7 @@
#include "cpu.h"
#include "chardev/char-fe.h"
#include "exec/helper-proto.h"
+#include "exec/target_page.h"
#include "semihosting/semihost.h"
#include "semihosting/uaccess.h"
#include "qapi/error.h"
generated by cgit v1.1 at 2025-04-30 17:03:53 +0000