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-rw-r--r--target/sh4/cpu-param.h2
-rw-r--r--target/sh4/cpu.c14
-rw-r--r--target/sh4/cpu.h6
-rw-r--r--target/sh4/helper.c1
-rw-r--r--target/sh4/op_helper.c2
-rw-r--r--target/sh4/translate.c37
6 files changed, 31 insertions, 31 deletions
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index 2b6e11d..f328715 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,4 +16,6 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
+#define TARGET_INSN_START_EXTRA_WORDS 1
+
#endif
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
index ce84bdf..57d7b5f 100644
--- a/target/sh4/cpu.c
+++ b/target/sh4/cpu.c
@@ -177,7 +177,7 @@ static void sh7750r_cpu_initfn(Object *obj)
env->features = SH_FEATURE_BCR3_AND_BCR4;
}
-static void sh7750r_class_init(ObjectClass *oc, void *data)
+static void sh7750r_class_init(ObjectClass *oc, const void *data)
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
@@ -194,7 +194,7 @@ static void sh7751r_cpu_initfn(Object *obj)
env->features = SH_FEATURE_BCR3_AND_BCR4;
}
-static void sh7751r_class_init(ObjectClass *oc, void *data)
+static void sh7751r_class_init(ObjectClass *oc, const void *data)
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
@@ -211,7 +211,7 @@ static void sh7785_cpu_initfn(Object *obj)
env->features = SH_FEATURE_SH4A;
}
-static void sh7785_class_init(ObjectClass *oc, void *data)
+static void sh7785_class_init(ObjectClass *oc, const void *data)
{
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
@@ -262,10 +262,15 @@ static const struct SysemuCPUOps sh4_sysemu_ops = {
#include "accel/tcg/cpu-ops.h"
static const TCGCPUOps superh_tcg_ops = {
+ /* MTTCG not yet supported: require strict ordering */
+ .guest_default_memory_order = TCG_MO_ALL,
+ .mttcg_supported = false,
+
.initialize = sh4_translate_init,
.translate_code = sh4_translate_code,
.synchronize_from_tb = superh_cpu_synchronize_from_tb,
.restore_state_to_opc = superh_restore_state_to_opc,
+ .mmu_index = sh4_cpu_mmu_index,
#ifndef CONFIG_USER_ONLY
.tlb_fill = superh_cpu_tlb_fill,
@@ -277,7 +282,7 @@ static const TCGCPUOps superh_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
-static void superh_cpu_class_init(ObjectClass *oc, void *data)
+static void superh_cpu_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
@@ -291,7 +296,6 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
&scc->parent_phases);
cc->class_by_name = superh_cpu_class_by_name;
- cc->mmu_index = sh4_cpu_mmu_index;
cc->dump_state = superh_cpu_dump_state;
cc->set_pc = superh_cpu_set_pc;
cc->get_pc = superh_cpu_get_pc;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index d536d5d..906f99d 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -21,7 +21,9 @@
#define SH4_CPU_H
#include "cpu-qom.h"
+#include "exec/cpu-common.h"
#include "exec/cpu-defs.h"
+#include "exec/cpu-interrupt.h"
#include "qemu/cpu-float.h"
/* CPU Subtypes */
@@ -125,8 +127,6 @@ typedef struct tlb_t {
#define UTLB_SIZE 64
#define ITLB_SIZE 4
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
enum sh_features {
SH_FEATURE_SH4A = 1,
SH_FEATURE_BCR3_AND_BCR4 = 2,
@@ -286,8 +286,6 @@ void cpu_load_tlb(CPUSH4State * env);
/* MMU modes definitions */
#define MMU_USER_IDX 1
-#include "exec/cpu-all.h"
-
/* MMU control register */
#define MMUCR 0x1F000010
#define MMUCR_AT (1<<0)
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 7567e6c..b41d14d 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -23,6 +23,7 @@
#include "exec/cputlb.h"
#include "exec/exec-all.h"
#include "exec/page-protection.h"
+#include "exec/target_page.h"
#include "exec/log.h"
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
index 99394b7..e7fcad3 100644
--- a/target/sh4/op_helper.c
+++ b/target/sh4/op_helper.c
@@ -20,7 +20,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
#include "fpu/softfloat.h"
#ifndef CONFIG_USER_ONLY
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 57b972e..712117b 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -25,6 +25,7 @@
#include "exec/helper-gen.h"
#include "exec/translation-block.h"
#include "exec/translator.h"
+#include "exec/target_page.h"
#include "exec/log.h"
#include "qemu/qemu-print.h"
@@ -694,14 +695,8 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4));
return;
case 0x300e: /* addc Rm,Rn */
- {
- TCGv t0, t1;
- t0 = tcg_constant_tl(0);
- t1 = tcg_temp_new();
- tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
- tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
- REG(B11_8), t0, t1, cpu_sr_t);
- }
+ tcg_gen_addcio_i32(REG(B11_8), cpu_sr_t,
+ REG(B11_8), REG(B7_4), cpu_sr_t);
return;
case 0x300f: /* addv Rm,Rn */
{
@@ -1939,16 +1934,16 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
NEXT_INSN;
switch (ctx->opcode & 0xf00f) {
case 0x300c: /* add Rm,Rn */
- op_opc = INDEX_op_add_i32;
+ op_opc = INDEX_op_add;
goto do_reg_op;
case 0x2009: /* and Rm,Rn */
- op_opc = INDEX_op_and_i32;
+ op_opc = INDEX_op_and;
goto do_reg_op;
case 0x200a: /* xor Rm,Rn */
- op_opc = INDEX_op_xor_i32;
+ op_opc = INDEX_op_xor;
goto do_reg_op;
case 0x200b: /* or Rm,Rn */
- op_opc = INDEX_op_or_i32;
+ op_opc = INDEX_op_or;
do_reg_op:
/* The operation register should be as expected, and the
other input cannot depend on the load. */
@@ -1975,7 +1970,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
goto fail;
}
op_dst = B11_8;
- op_opc = INDEX_op_xor_i32;
+ op_opc = INDEX_op_xor;
op_arg = tcg_constant_i32(-1);
break;
@@ -1983,7 +1978,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
if (op_dst != B11_8 || mv_src >= 0) {
goto fail;
}
- op_opc = INDEX_op_add_i32;
+ op_opc = INDEX_op_add;
op_arg = tcg_constant_i32(B7_0s);
break;
@@ -1994,7 +1989,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) {
goto fail;
}
- op_opc = INDEX_op_setcond_i32; /* placeholder */
+ op_opc = INDEX_op_setcond; /* placeholder */
op_src = (ld_dst == B11_8 ? B7_4 : B11_8);
op_arg = REG(op_src);
@@ -2029,7 +2024,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) {
goto fail;
}
- op_opc = INDEX_op_setcond_i32;
+ op_opc = INDEX_op_setcond;
op_arg = tcg_constant_i32(0);
NEXT_INSN;
@@ -2086,7 +2081,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
ctx->memidx, ld_mop);
break;
- case INDEX_op_add_i32:
+ case INDEX_op_add:
if (op_dst != st_src) {
goto fail;
}
@@ -2104,7 +2099,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
break;
- case INDEX_op_and_i32:
+ case INDEX_op_and:
if (op_dst != st_src) {
goto fail;
}
@@ -2118,7 +2113,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
break;
- case INDEX_op_or_i32:
+ case INDEX_op_or:
if (op_dst != st_src) {
goto fail;
}
@@ -2132,7 +2127,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
break;
- case INDEX_op_xor_i32:
+ case INDEX_op_xor:
if (op_dst != st_src) {
goto fail;
}
@@ -2146,7 +2141,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
}
break;
- case INDEX_op_setcond_i32:
+ case INDEX_op_setcond:
if (st_src == ld_dst) {
goto fail;
}
generated by cgit v1.1 at 2025-05-04 08:21:58 +0000