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Diffstat (limited to 'target/rx/translate.c')
-rw-r--r--target/rx/translate.c463
1 files changed, 234 insertions, 229 deletions
diff --git a/target/rx/translate.c b/target/rx/translate.c
index bbda703..ef865f1 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -20,7 +20,6 @@
#include "qemu/bswap.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
-#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
@@ -41,8 +40,8 @@ typedef struct DisasContext {
} DisasContext;
typedef struct DisasCompare {
- TCGv value;
- TCGv temp;
+ TCGv_i32 value;
+ TCGv_i32 temp;
TCGCond cond;
} DisasCompare;
@@ -64,15 +63,20 @@ const char *rx_crname(uint8_t cr)
#define DISAS_EXIT DISAS_TARGET_2
/* global register indexes */
-static TCGv cpu_regs[16];
-static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c;
-static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl;
-static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp;
-static TCGv cpu_fintv, cpu_intb, cpu_pc;
+static TCGv_i32 cpu_regs[16];
+static TCGv_i32 cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c;
+static TCGv_i32 cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl;
+static TCGv_i32 cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp;
+static TCGv_i32 cpu_fintv, cpu_intb, cpu_pc;
static TCGv_i64 cpu_acc;
#define cpu_sp cpu_regs[0]
+static inline MemOp mo_endian(DisasContext *dc)
+{
+ return MO_LE;
+}
+
/* decoder helper */
static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
int i, int n)
@@ -86,7 +90,7 @@ static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn,
static uint32_t li(DisasContext *ctx, int sz)
{
- target_ulong addr;
+ vaddr addr;
uint32_t tmp;
CPURXState *env = ctx->env;
addr = ctx->base.pc_next;
@@ -148,12 +152,12 @@ void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
-static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
+static void gen_goto_tb(DisasContext *dc, unsigned tb_slot_idx, vaddr dest)
{
if (translator_use_goto_tb(&dc->base, dest)) {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
tcg_gen_movi_i32(cpu_pc, dest);
- tcg_gen_exit_tb(dc->base.tb, n);
+ tcg_gen_exit_tb(dc->base.tb, tb_slot_idx);
} else {
tcg_gen_movi_i32(cpu_pc, dest);
tcg_gen_lookup_and_goto_ptr();
@@ -162,34 +166,34 @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
}
/* generic load wrapper */
-static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem)
+static void rx_gen_ld(DisasContext *ctx, MemOp size, TCGv_i32 reg, TCGv_i32 mem)
{
- tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
+ tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | mo_endian(ctx));
}
/* unsigned load wrapper */
-static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem)
+static void rx_gen_ldu(DisasContext *ctx, MemOp size, TCGv_i32 reg, TCGv_i32 mem)
{
- tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE);
+ tcg_gen_qemu_ld_i32(reg, mem, 0, size | mo_endian(ctx));
}
/* generic store wrapper */
-static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem)
+static void rx_gen_st(DisasContext *ctx, MemOp size, TCGv_i32 reg, TCGv_i32 mem)
{
- tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
+ tcg_gen_qemu_st_i32(reg, mem, 0, size | mo_endian(ctx));
}
/* [ri, rb] */
-static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem,
- int size, int ri, int rb)
+static void rx_gen_regindex(DisasContext *ctx, TCGv_i32 mem,
+ int size, int ri, int rb)
{
tcg_gen_shli_i32(mem, cpu_regs[ri], size);
tcg_gen_add_i32(mem, mem, cpu_regs[rb]);
}
/* dsp[reg] */
-static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem,
- int ld, int size, int reg)
+static TCGv_i32 rx_index_addr(DisasContext *ctx, TCGv_i32 mem,
+ int ld, int size, int reg)
{
uint32_t dsp;
@@ -219,15 +223,15 @@ static inline MemOp mi_to_mop(unsigned mi)
}
/* load source operand */
-static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem,
- int ld, int mi, int rs)
+static TCGv_i32 rx_load_source(DisasContext *ctx, TCGv_i32 mem,
+ int ld, int mi, int rs)
{
- TCGv addr;
+ TCGv_i32 addr;
MemOp mop;
if (ld < 3) {
mop = mi_to_mop(mi);
addr = rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs);
- tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE);
+ tcg_gen_qemu_ld_i32(mem, addr, 0, mop | mo_endian(ctx));
return mem;
} else {
return cpu_regs[rs];
@@ -316,7 +320,7 @@ static void psw_cond(DisasCompare *dc, uint32_t cond)
}
}
-static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc)
+static void move_from_cr(DisasContext *ctx, TCGv_i32 ret, int cr, uint32_t pc)
{
switch (cr) {
case 0: /* PSW */
@@ -362,7 +366,7 @@ static void move_from_cr(DisasContext *ctx, TCGv ret, int cr, uint32_t pc)
}
}
-static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
+static void move_to_cr(DisasContext *ctx, TCGv_i32 val, int cr)
{
if (cr >= 8 && !is_privileged(ctx, 0)) {
/* Some control registers can only be written in privileged mode. */
@@ -415,35 +419,35 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int cr)
}
}
-static void push(TCGv val)
+static void push(DisasContext *ctx, TCGv_i32 val)
{
tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
- rx_gen_st(MO_32, val, cpu_sp);
+ rx_gen_st(ctx, MO_32, val, cpu_sp);
}
-static void pop(TCGv ret)
+static void pop(DisasContext *ctx, TCGv_i32 ret)
{
- rx_gen_ld(MO_32, ret, cpu_sp);
+ rx_gen_ld(ctx, MO_32, ret, cpu_sp);
tcg_gen_addi_i32(cpu_sp, cpu_sp, 4);
}
/* mov.<bwl> rs,dsp5[rd] */
static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
- rx_gen_st(a->sz, cpu_regs[a->rs], mem);
+ rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem);
return true;
}
/* mov.<bwl> dsp5[rs],rd */
static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
- rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
+ rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem);
return true;
}
@@ -460,31 +464,31 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
/* mov.<bwl> #imm, dsp[rd] */
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{
- TCGv imm, mem;
+ TCGv_i32 imm, mem;
imm = tcg_constant_i32(a->imm);
- mem = tcg_temp_new();
+ mem = tcg_temp_new_i32();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
- rx_gen_st(a->sz, imm, mem);
+ rx_gen_st(ctx, a->sz, imm, mem);
return true;
}
/* mov.<bwl> [ri,rb],rd */
static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
- rx_gen_ld(a->sz, cpu_regs[a->rd], mem);
+ rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], mem);
return true;
}
/* mov.<bwl> rd,[ri,rb] */
static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
- rx_gen_st(a->sz, cpu_regs[a->rs], mem);
+ rx_gen_st(ctx, a->sz, cpu_regs[a->rs], mem);
return true;
}
@@ -494,7 +498,7 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a)
/* mov.<bwl> rs,rd */
static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
{
- TCGv tmp, mem, addr;
+ TCGv_i32 tmp, mem, addr;
if (a->lds == 3 && a->ldd == 3) {
/* mov.<bwl> rs,rd */
@@ -502,22 +506,22 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
return true;
}
- mem = tcg_temp_new();
+ mem = tcg_temp_new_i32();
if (a->lds == 3) {
/* mov.<bwl> rs,dsp[rd] */
addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs);
- rx_gen_st(a->sz, cpu_regs[a->rd], addr);
+ rx_gen_st(ctx, a->sz, cpu_regs[a->rd], addr);
} else if (a->ldd == 3) {
/* mov.<bwl> dsp[rs],rd */
addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
- rx_gen_ld(a->sz, cpu_regs[a->rd], addr);
+ rx_gen_ld(ctx, a->sz, cpu_regs[a->rd], addr);
} else {
/* mov.<bwl> dsp[rs],dsp[rd] */
- tmp = tcg_temp_new();
+ tmp = tcg_temp_new_i32();
addr = rx_index_addr(ctx, mem, a->lds, a->sz, a->rs);
- rx_gen_ld(a->sz, tmp, addr);
+ rx_gen_ld(ctx, a->sz, tmp, addr);
addr = rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd);
- rx_gen_st(a->sz, tmp, addr);
+ rx_gen_st(ctx, a->sz, tmp, addr);
}
return true;
}
@@ -526,13 +530,13 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a)
/* mov.<bwl> rs,[-rd] */
static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
{
- TCGv val;
- val = tcg_temp_new();
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
tcg_gen_mov_i32(val, cpu_regs[a->rs]);
if (a->ad == 1) {
tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
- rx_gen_st(a->sz, val, cpu_regs[a->rd]);
+ rx_gen_st(ctx, a->sz, val, cpu_regs[a->rd]);
if (a->ad == 0) {
tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
@@ -543,12 +547,12 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a)
/* mov.<bwl> [-rd],rs */
static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
{
- TCGv val;
- val = tcg_temp_new();
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
if (a->ad == 1) {
tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
- rx_gen_ld(a->sz, val, cpu_regs[a->rd]);
+ rx_gen_ld(ctx, a->sz, val, cpu_regs[a->rd]);
if (a->ad == 0) {
tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
@@ -560,10 +564,10 @@ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a)
/* movu.<bw> dsp[rs],rd */
static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz);
- rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
+ rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem);
return true;
}
@@ -577,10 +581,10 @@ static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a)
/* movu.<bw> [ri,rb],rd */
static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
{
- TCGv mem;
- mem = tcg_temp_new();
+ TCGv_i32 mem;
+ mem = tcg_temp_new_i32();
rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb);
- rx_gen_ldu(a->sz, cpu_regs[a->rd], mem);
+ rx_gen_ldu(ctx, a->sz, cpu_regs[a->rd], mem);
return true;
}
@@ -588,12 +592,12 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a)
/* mov.<bw> [-rd],rs */
static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a)
{
- TCGv val;
- val = tcg_temp_new();
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
if (a->ad == 1) {
tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
- rx_gen_ldu(a->sz, val, cpu_regs[a->rd]);
+ rx_gen_ldu(ctx, a->sz, val, cpu_regs[a->rd]);
if (a->ad == 0) {
tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz);
}
@@ -618,9 +622,9 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)
/* popc cr */
static bool trans_POPC(DisasContext *ctx, arg_POPC *a)
{
- TCGv val;
- val = tcg_temp_new();
- pop(val);
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
+ pop(ctx, val);
move_to_cr(ctx, val, a->cr);
return true;
}
@@ -635,7 +639,7 @@ static bool trans_POPM(DisasContext *ctx, arg_POPM *a)
}
r = a->rd;
while (r <= a->rd2 && r < 16) {
- pop(cpu_regs[r++]);
+ pop(ctx, cpu_regs[r++]);
}
return true;
}
@@ -644,34 +648,34 @@ static bool trans_POPM(DisasContext *ctx, arg_POPM *a)
/* push.<bwl> rs */
static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
{
- TCGv val;
- val = tcg_temp_new();
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
tcg_gen_mov_i32(val, cpu_regs[a->rs]);
tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
- rx_gen_st(a->sz, val, cpu_sp);
+ rx_gen_st(ctx, a->sz, val, cpu_sp);
return true;
}
/* push.<bwl> dsp[rs] */
static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a)
{
- TCGv mem, val, addr;
- mem = tcg_temp_new();
- val = tcg_temp_new();
+ TCGv_i32 mem, val, addr;
+ mem = tcg_temp_new_i32();
+ val = tcg_temp_new_i32();
addr = rx_index_addr(ctx, mem, a->ld, a->sz, a->rs);
- rx_gen_ld(a->sz, val, addr);
+ rx_gen_ld(ctx, a->sz, val, addr);
tcg_gen_subi_i32(cpu_sp, cpu_sp, 4);
- rx_gen_st(a->sz, val, cpu_sp);
+ rx_gen_st(ctx, a->sz, val, cpu_sp);
return true;
}
/* pushc rx */
static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a)
{
- TCGv val;
- val = tcg_temp_new();
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
move_from_cr(ctx, val, a->cr, ctx->pc);
- push(val);
+ push(ctx, val);
return true;
}
@@ -686,7 +690,7 @@ static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a)
}
r = a->rs2;
while (r >= a->rs && r >= 0) {
- push(cpu_regs[r--]);
+ push(ctx, cpu_regs[r--]);
}
return true;
}
@@ -694,8 +698,8 @@ static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a)
/* xchg rs,rd */
static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a)
{
- TCGv tmp;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp;
+ tmp = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp, cpu_regs[a->rs]);
tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]);
tcg_gen_mov_i32(cpu_regs[a->rd], tmp);
@@ -705,8 +709,8 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a)
/* xchg dsp[rs].<mi>,rd */
static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a)
{
- TCGv mem, addr;
- mem = tcg_temp_new();
+ TCGv_i32 mem, addr;
+ mem = tcg_temp_new_i32();
switch (a->mi) {
case 0: /* dsp[rs].b */
case 1: /* dsp[rs].w */
@@ -725,10 +729,10 @@ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a)
return true;
}
-static inline void stcond(TCGCond cond, int rd, int imm)
+static void stcond(TCGCond cond, int rd, int imm)
{
- TCGv z;
- TCGv _imm;
+ TCGv_i32 z;
+ TCGv_i32 _imm;
z = tcg_constant_i32(0);
_imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
@@ -754,15 +758,15 @@ static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a)
static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a)
{
DisasCompare dc;
- TCGv val, mem, addr;
- dc.temp = tcg_temp_new();
+ TCGv_i32 val, mem, addr;
+ dc.temp = tcg_temp_new_i32();
psw_cond(&dc, a->cd);
if (a->ld < 3) {
- val = tcg_temp_new();
- mem = tcg_temp_new();
+ val = tcg_temp_new_i32();
+ mem = tcg_temp_new_i32();
tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0);
addr = rx_index_addr(ctx, mem, a->sz, a->ld, a->rd);
- rx_gen_st(a->sz, val, addr);
+ rx_gen_st(ctx, a->sz, val, addr);
} else {
tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0);
}
@@ -773,7 +777,7 @@ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a)
static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a)
{
tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2);
- pop(cpu_pc);
+ pop(ctx, cpu_pc);
ctx->base.is_jmp = DISAS_JUMP;
return true;
}
@@ -793,42 +797,42 @@ static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a)
tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2);
dst = a->rd;
while (dst <= a->rd2 && dst < 16) {
- pop(cpu_regs[dst++]);
+ pop(ctx, cpu_regs[dst++]);
}
- pop(cpu_pc);
+ pop(ctx, cpu_pc);
ctx->base.is_jmp = DISAS_JUMP;
return true;
}
-typedef void (*op2fn)(TCGv ret, TCGv arg1);
-typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2);
+typedef void (*op2fn)(TCGv_i32 ret, TCGv_i32 arg1);
+typedef void (*op3fn)(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
-static inline void rx_gen_op_rr(op2fn opr, int dst, int src)
+static void rx_gen_op_rr(op2fn opr, int dst, int src)
{
opr(cpu_regs[dst], cpu_regs[src]);
}
-static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
+static void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
{
opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]);
}
-static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
+static void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{
- TCGv imm = tcg_constant_i32(src2);
+ TCGv_i32 imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm);
}
-static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx,
- int dst, int src, int ld, int mi)
+static void rx_gen_op_mr(op3fn opr, DisasContext *ctx,
+ int dst, int src, int ld, int mi)
{
- TCGv val, mem;
- mem = tcg_temp_new();
+ TCGv_i32 val, mem;
+ mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, ld, mi, src);
opr(cpu_regs[dst], cpu_regs[dst], val);
}
-static void rx_and(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_and(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
@@ -858,7 +862,7 @@ static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a)
return true;
}
-static void rx_or(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_or(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_or_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
@@ -888,7 +892,7 @@ static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a)
return true;
}
-static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_xor(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_xor_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
@@ -910,7 +914,7 @@ static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a)
return true;
}
-static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_tst(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_and_i32(cpu_psw_s, arg1, arg2);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s);
@@ -931,7 +935,7 @@ static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a)
return true;
}
-static void rx_not(TCGv ret, TCGv arg1)
+static void rx_not(TCGv_i32 ret, TCGv_i32 arg1)
{
tcg_gen_not_i32(ret, arg1);
tcg_gen_mov_i32(cpu_psw_z, ret);
@@ -946,7 +950,7 @@ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a)
return true;
}
-static void rx_neg(TCGv ret, TCGv arg1)
+static void rx_neg(TCGv_i32 ret, TCGv_i32 arg1)
{
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000);
tcg_gen_neg_i32(ret, arg1);
@@ -965,9 +969,9 @@ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a)
}
/* ret = arg1 + arg2 + psw_c */
-static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_adc(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv z = tcg_constant_i32(0);
+ TCGv_i32 z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
@@ -1003,9 +1007,9 @@ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a)
}
/* ret = arg1 + arg2 */
-static void rx_add(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_add(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv z = tcg_constant_i32(0);
+ TCGv_i32 z = tcg_constant_i32(0);
tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z);
tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1);
tcg_gen_xor_i32(cpu_psw_z, arg1, arg2);
@@ -1038,7 +1042,7 @@ static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a)
}
/* ret = arg1 - arg2 */
-static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_sub(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_sub_i32(cpu_psw_s, arg1, arg2);
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2);
@@ -1052,17 +1056,17 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2)
}
}
-static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2)
+static void rx_cmp(TCGv_i32 dummy, TCGv_i32 arg1, TCGv_i32 arg2)
{
rx_sub(NULL, arg1, arg2);
}
/* ret = arg1 - arg2 - !psw_c */
/* -> ret = arg1 + ~arg2 + psw_c */
-static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_sbb(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
- TCGv temp;
- temp = tcg_temp_new();
+ TCGv_i32 temp;
+ temp = tcg_temp_new_i32();
tcg_gen_not_i32(temp, arg2);
rx_adc(ret, arg1, temp);
}
@@ -1188,7 +1192,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{
- TCGv imm = tcg_constant_i32(a->imm);
+ TCGv_i32 imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1201,11 +1205,11 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
/* emul dsp[rs], rd */
static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
{
- TCGv val, mem;
+ TCGv_i32 val, mem;
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
- mem = tcg_temp_new();
+ mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
cpu_regs[a->rd], val);
@@ -1215,7 +1219,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{
- TCGv imm = tcg_constant_i32(a->imm);
+ TCGv_i32 imm = tcg_constant_i32(a->imm);
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
@@ -1228,23 +1232,23 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
/* emulu dsp[rs], rd */
static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a)
{
- TCGv val, mem;
+ TCGv_i32 val, mem;
if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
}
- mem = tcg_temp_new();
+ mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15],
cpu_regs[a->rd], val);
return true;
}
-static void rx_div(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_div(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
gen_helper_div(ret, tcg_env, arg1, arg2);
}
-static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2)
+static void rx_divu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
gen_helper_divu(ret, tcg_env, arg1, arg2);
}
@@ -1284,8 +1288,8 @@ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a)
/* shll #imm:5, rs2, rd */
static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
{
- TCGv tmp;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp;
+ tmp = tcg_temp_new_i32();
if (a->imm) {
tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm);
tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm);
@@ -1307,14 +1311,14 @@ static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a)
static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
{
TCGLabel *noshift, *done;
- TCGv count, tmp;
+ TCGv_i32 count, tmp;
noshift = gen_new_label();
done = gen_new_label();
/* if (cpu_regs[a->rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift);
- count = tcg_temp_new();
- tmp = tcg_temp_new();
+ count = tcg_temp_new_i32();
+ tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31);
tcg_gen_sub_i32(count, tcg_constant_i32(32), tmp);
tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count);
@@ -1335,10 +1339,10 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a)
return true;
}
-static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm,
- unsigned int alith)
+static void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm,
+ unsigned int alith)
{
- static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
+ static void (* const gen_sXri[])(TCGv_i32 ret, TCGv_i32 arg1, int arg2) = {
tcg_gen_shri_i32, tcg_gen_sari_i32,
};
tcg_debug_assert(alith < 2);
@@ -1355,20 +1359,21 @@ static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm,
tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]);
}
-static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith)
+static void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith)
{
TCGLabel *noshift, *done;
- TCGv count;
- static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) = {
+ TCGv_i32 count;
+ static void (* const gen_sXri[])(TCGv_i32 ret, TCGv_i32 arg1, int arg2) = {
tcg_gen_shri_i32, tcg_gen_sari_i32,
};
- static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) = {
+ static void (* const gen_sXr[])(TCGv_i32 ret,
+ TCGv_i32 arg1, TCGv_i32 arg2) = {
tcg_gen_shr_i32, tcg_gen_sar_i32,
};
tcg_debug_assert(alith < 2);
noshift = gen_new_label();
done = gen_new_label();
- count = tcg_temp_new();
+ count = tcg_temp_new_i32();
/* if (cpu_regs[rs]) { */
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift);
tcg_gen_andi_i32(count, cpu_regs[rs], 31);
@@ -1420,8 +1425,8 @@ static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a)
/* rolc rd */
static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a)
{
- TCGv tmp;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp;
+ tmp = tcg_temp_new_i32();
tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31);
tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c);
@@ -1434,8 +1439,8 @@ static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a)
/* rorc rd */
static bool trans_RORC(DisasContext *ctx, arg_RORC *a)
{
- TCGv tmp;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp;
+ tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001);
tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1);
tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31);
@@ -1448,7 +1453,7 @@ static bool trans_RORC(DisasContext *ctx, arg_RORC *a)
enum {ROTR = 0, ROTL = 1};
enum {ROT_IMM = 0, ROT_REG = 1};
-static inline void rx_rot(int ir, int dir, int rd, int src)
+static void rx_rot(int ir, int dir, int rd, int src)
{
switch (dir) {
case ROTL:
@@ -1510,8 +1515,8 @@ static bool trans_REVL(DisasContext *ctx, arg_REVL *a)
/* revw rs, rd */
static bool trans_REVW(DisasContext *ctx, arg_REVW *a)
{
- TCGv tmp;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp;
+ tmp = tcg_temp_new_i32();
tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff);
tcg_gen_shli_i32(tmp, tmp, 8);
tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8);
@@ -1528,7 +1533,7 @@ static void rx_bcnd_main(DisasContext *ctx, int cd, int dst)
switch (cd) {
case 0 ... 13:
- dc.temp = tcg_temp_new();
+ dc.temp = tcg_temp_new_i32();
psw_cond(&dc, cd);
t = gen_new_label();
done = gen_new_label();
@@ -1583,10 +1588,10 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
return true;
}
-static inline void rx_save_pc(DisasContext *ctx)
+static void rx_save_pc(DisasContext *ctx)
{
- TCGv pc = tcg_constant_i32(ctx->base.pc_next);
- push(pc);
+ TCGv_i32 pc = tcg_constant_i32(ctx->base.pc_next);
+ push(ctx, pc);
}
/* jmp rs */
@@ -1627,7 +1632,7 @@ static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a)
/* rts */
static bool trans_RTS(DisasContext *ctx, arg_RTS *a)
{
- pop(cpu_pc);
+ pop(ctx, cpu_pc);
ctx->base.is_jmp = DISAS_JUMP;
return true;
}
@@ -1668,7 +1673,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
#define STRING(op) \
do { \
- TCGv size = tcg_constant_i32(a->sz); \
+ TCGv_i32 size = tcg_constant_i32(a->sz); \
gen_helper_##op(tcg_env, size); \
} while (0)
@@ -1799,7 +1804,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{
- TCGv imm = tcg_constant_i32(a->imm + 1);
+ TCGv_i32 imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(tcg_env, imm);
return true;
}
@@ -1807,8 +1812,8 @@ static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
/* sat rd */
static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{
- TCGv tmp, z;
- tmp = tcg_temp_new();
+ TCGv_i32 tmp, z;
+ tmp = tcg_temp_new_i32();
z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
@@ -1831,7 +1836,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
- TCGv imm = tcg_constant_i32(li(ctx, 0)); \
+ TCGv_i32 imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], imm); \
return true; \
@@ -1839,8 +1844,8 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _mr)(DisasContext *ctx, \
cat3(arg_, name, _mr) * a) \
{ \
- TCGv val, mem; \
- mem = tcg_temp_new(); \
+ TCGv_i32 val, mem; \
+ mem = tcg_temp_new_i32(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
gen_helper_##op(cpu_regs[a->rd], tcg_env, \
cpu_regs[a->rd], val); \
@@ -1850,8 +1855,8 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
#define FCONVOP(name, op) \
static bool trans_##name(DisasContext *ctx, arg_##name * a) \
{ \
- TCGv val, mem; \
- mem = tcg_temp_new(); \
+ TCGv_i32 val, mem; \
+ mem = tcg_temp_new_i32(); \
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \
gen_helper_##op(cpu_regs[a->rd], tcg_env, val); \
return true; \
@@ -1865,7 +1870,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
- TCGv imm = tcg_constant_i32(li(ctx, 0));
+ TCGv_i32 imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm);
return true;
}
@@ -1874,8 +1879,8 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
/* fcmp rs, rd */
static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
{
- TCGv val, mem;
- mem = tcg_temp_new();
+ TCGv_i32 val, mem;
+ mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val);
return true;
@@ -1888,70 +1893,70 @@ FCONVOP(ROUND, round)
/* itof dsp[rs], rd */
static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a)
{
- TCGv val, mem;
- mem = tcg_temp_new();
+ TCGv_i32 val, mem;
+ mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
gen_helper_itof(cpu_regs[a->rd], tcg_env, val);
return true;
}
-static void rx_bsetm(TCGv mem, TCGv mask)
+static void rx_bsetm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask)
{
- TCGv val;
- val = tcg_temp_new();
- rx_gen_ld(MO_8, val, mem);
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
+ rx_gen_ld(ctx, MO_8, val, mem);
tcg_gen_or_i32(val, val, mask);
- rx_gen_st(MO_8, val, mem);
+ rx_gen_st(ctx, MO_8, val, mem);
}
-static void rx_bclrm(TCGv mem, TCGv mask)
+static void rx_bclrm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask)
{
- TCGv val;
- val = tcg_temp_new();
- rx_gen_ld(MO_8, val, mem);
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
+ rx_gen_ld(ctx, MO_8, val, mem);
tcg_gen_andc_i32(val, val, mask);
- rx_gen_st(MO_8, val, mem);
+ rx_gen_st(ctx, MO_8, val, mem);
}
-static void rx_btstm(TCGv mem, TCGv mask)
+static void rx_btstm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask)
{
- TCGv val;
- val = tcg_temp_new();
- rx_gen_ld(MO_8, val, mem);
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
+ rx_gen_ld(ctx, MO_8, val, mem);
tcg_gen_and_i32(val, val, mask);
tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
}
-static void rx_bnotm(TCGv mem, TCGv mask)
+static void rx_bnotm(DisasContext *ctx, TCGv_i32 mem, TCGv_i32 mask)
{
- TCGv val;
- val = tcg_temp_new();
- rx_gen_ld(MO_8, val, mem);
+ TCGv_i32 val;
+ val = tcg_temp_new_i32();
+ rx_gen_ld(ctx, MO_8, val, mem);
tcg_gen_xor_i32(val, val, mask);
- rx_gen_st(MO_8, val, mem);
+ rx_gen_st(ctx, MO_8, val, mem);
}
-static void rx_bsetr(TCGv reg, TCGv mask)
+static void rx_bsetr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask)
{
tcg_gen_or_i32(reg, reg, mask);
}
-static void rx_bclrr(TCGv reg, TCGv mask)
+static void rx_bclrr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask)
{
tcg_gen_andc_i32(reg, reg, mask);
}
-static inline void rx_btstr(TCGv reg, TCGv mask)
+static void rx_btstr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask)
{
- TCGv t0;
- t0 = tcg_temp_new();
+ TCGv_i32 t0;
+ t0 = tcg_temp_new_i32();
tcg_gen_and_i32(t0, reg, mask);
tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0);
tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c);
}
-static inline void rx_bnotr(TCGv reg, TCGv mask)
+static void rx_bnotr(DisasContext *ctx, TCGv_i32 reg, TCGv_i32 mask)
{
tcg_gen_xor_i32(reg, reg, mask);
}
@@ -1960,43 +1965,43 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
static bool cat3(trans_, name, _im)(DisasContext *ctx, \
cat3(arg_, name, _im) * a) \
{ \
- TCGv mask, mem, addr; \
- mem = tcg_temp_new(); \
+ TCGv_i32 mask, mem, addr; \
+ mem = tcg_temp_new_i32(); \
mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
- cat3(rx_, op, m)(addr, mask); \
+ cat3(rx_, op, m)(ctx, addr, mask); \
return true; \
} \
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \
{ \
- TCGv mask; \
+ TCGv_i32 mask; \
mask = tcg_constant_i32(1 << a->imm); \
- cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
+ cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \
return true; \
} \
static bool cat3(trans_, name, _rr)(DisasContext *ctx, \
cat3(arg_, name, _rr) * a) \
{ \
- TCGv mask, b; \
- mask = tcg_temp_new(); \
- b = tcg_temp_new(); \
+ TCGv_i32 mask, b; \
+ mask = tcg_temp_new_i32(); \
+ b = tcg_temp_new_i32(); \
tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
- cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
+ cat3(rx_, op, r)(ctx, cpu_regs[a->rd], mask); \
return true; \
} \
static bool cat3(trans_, name, _rm)(DisasContext *ctx, \
cat3(arg_, name, _rm) * a) \
{ \
- TCGv mask, mem, addr, b; \
- mask = tcg_temp_new(); \
- b = tcg_temp_new(); \
+ TCGv_i32 mask, mem, addr, b; \
+ mask = tcg_temp_new_i32(); \
+ b = tcg_temp_new_i32(); \
tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \
tcg_gen_shl_i32(mask, tcg_constant_i32(1), b); \
- mem = tcg_temp_new(); \
+ mem = tcg_temp_new_i32(); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
- cat3(rx_, op, m)(addr, mask); \
+ cat3(rx_, op, m)(ctx, addr, mask); \
return true; \
}
@@ -2005,12 +2010,12 @@ BITOP(BCLR, bclr)
BITOP(BTST, btst)
BITOP(BNOT, bnot)
-static inline void bmcnd_op(TCGv val, TCGCond cond, int pos)
+static void bmcnd_op(TCGv_i32 val, TCGCond cond, int pos)
{
- TCGv bit;
+ TCGv_i32 bit;
DisasCompare dc;
- dc.temp = tcg_temp_new();
- bit = tcg_temp_new();
+ dc.temp = tcg_temp_new_i32();
+ bit = tcg_temp_new_i32();
psw_cond(&dc, cond);
tcg_gen_andi_i32(val, val, ~(1 << pos));
tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0);
@@ -2020,13 +2025,13 @@ static inline void bmcnd_op(TCGv val, TCGCond cond, int pos)
/* bmcnd #imm, dsp[rd] */
static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a)
{
- TCGv val, mem, addr;
- val = tcg_temp_new();
- mem = tcg_temp_new();
+ TCGv_i32 val, mem, addr;
+ val = tcg_temp_new_i32();
+ mem = tcg_temp_new_i32();
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rd);
- rx_gen_ld(MO_8, val, addr);
+ rx_gen_ld(ctx, MO_8, val, addr);
bmcnd_op(val, a->cd, a->imm);
- rx_gen_st(MO_8, val, addr);
+ rx_gen_st(ctx, MO_8, val, addr);
return true;
}
@@ -2046,7 +2051,7 @@ enum {
PSW_U = 9,
};
-static inline void clrsetpsw(DisasContext *ctx, int cb, int val)
+static void clrsetpsw(DisasContext *ctx, int cb, int val)
{
if (cb < 8) {
switch (cb) {
@@ -2114,7 +2119,7 @@ static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a)
/* mvtc #imm, rd */
static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{
- TCGv imm;
+ TCGv_i32 imm;
imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr);
@@ -2138,9 +2143,9 @@ static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a)
/* rtfi */
static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a)
{
- TCGv psw;
+ TCGv_i32 psw;
if (is_privileged(ctx, 1)) {
- psw = tcg_temp_new();
+ psw = tcg_temp_new_i32();
tcg_gen_mov_i32(cpu_pc, cpu_bpc);
tcg_gen_mov_i32(psw, cpu_bpsw);
gen_helper_set_psw_rte(tcg_env, psw);
@@ -2152,11 +2157,11 @@ static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a)
/* rte */
static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
{
- TCGv psw;
+ TCGv_i32 psw;
if (is_privileged(ctx, 1)) {
- psw = tcg_temp_new();
- pop(cpu_pc);
- pop(psw);
+ psw = tcg_temp_new_i32();
+ pop(ctx, cpu_pc);
+ pop(ctx, psw);
gen_helper_set_psw_rte(tcg_env, psw);
ctx->base.is_jmp = DISAS_EXIT;
}
@@ -2175,7 +2180,7 @@ static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
/* int #imm */
static bool trans_INT(DisasContext *ctx, arg_INT *a)
{
- TCGv vec;
+ TCGv_i32 vec;
tcg_debug_assert(a->imm < 0x100);
vec = tcg_constant_i32(a->imm);
generated by cgit v1.1 at 2025-10-17 15:49:26 +0000