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-rw-r--r--target/riscv/cpu.h4
-rw-r--r--target/riscv/insn_trans/trans_rvv.c.inc16
-rw-r--r--target/riscv/kvm/kvm-cpu.c8
-rw-r--r--target/riscv/monitor.c12
-rw-r--r--target/riscv/translate.c9
-rw-r--r--target/riscv/vector_helper.c32
6 files changed, 44 insertions, 37 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2c22664..4c13012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
*/
#define RISCV_UW2_ALWAYS_STORE_AMO 1
-#define RV(x) ((target_ulong)1 << (x - 'A'))
+#define RV(x) BIT(x - 'A')
/*
* Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
@@ -582,7 +582,7 @@ struct RISCVCPUClass {
RISCVCPUDef *def;
};
-static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
+static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext)
{
return (env->misa_ext & ext) != 0;
}
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f4b5460..2a48717 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3351,19 +3351,19 @@ static void load_element(TCGv_i64 dest, TCGv_ptr base,
/* offset of the idx element with base register r */
static uint32_t endian_ofs(DisasContext *s, int r, int idx)
{
-#if HOST_BIG_ENDIAN
- return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
-#else
- return vreg_ofs(s, r) + (idx << s->sew);
-#endif
+ if (HOST_BIG_ENDIAN) {
+ return vreg_ofs(s, r) + ((idx ^ (7 >> s->sew)) << s->sew);
+ } else {
+ return vreg_ofs(s, r) + (idx << s->sew);
+ }
}
/* adjust the index according to the endian */
static void endian_adjust(TCGv_i32 ofs, int sew)
{
-#if HOST_BIG_ENDIAN
- tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
-#endif
+ if (HOST_BIG_ENDIAN) {
+ tcg_gen_xori_i32(ofs, ofs, 7 >> sew);
+ }
}
/* Load idx >= VLMAX ? 0 : vreg[idx] */
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 187c2c9..0dd0d59 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -36,6 +36,7 @@
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "system/address-spaces.h"
+#include "system/memory.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/intc/riscv_imsic.h"
@@ -1369,7 +1370,7 @@ int kvm_riscv_sync_mpstate_to_kvm(RISCVCPU *cpu, int state)
return 0;
}
-int kvm_arch_put_registers(CPUState *cs, int level, Error **errp)
+int kvm_arch_put_registers(CPUState *cs, KvmPutState level, Error **errp)
{
int ret = 0;
@@ -1564,6 +1565,7 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
g_autofree uint8_t *buf = NULL;
RISCVCPU *cpu = RISCV_CPU(cs);
target_ulong num_bytes;
@@ -1602,9 +1604,9 @@ static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
exit(1);
}
- cpu_physical_memory_write(addr, buf, ret);
+ address_space_write(cs->as, addr, attrs, buf, ret);
} else {
- cpu_physical_memory_read(addr, buf, num_bytes);
+ address_space_read(cs->as, addr, attrs, buf, num_bytes);
ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
if (ret < 0) {
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 100005e..8a77476 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -23,6 +23,7 @@
#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
+#include "system/memory.h"
#ifdef TARGET_RISCV64
#define PTE_HEADER_FIELDS "vaddr paddr "\
@@ -77,11 +78,13 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
attr & PTE_D ? 'd' : '-');
}
-static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+static void walk_pte(Monitor *mon, AddressSpace *as,
+ hwaddr base, target_ulong start,
int level, int ptidxbits, int ptesize, int va_bits,
target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
target_ulong *last_size, int *last_attr)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
hwaddr pte_addr;
hwaddr paddr;
target_ulong last_start = -1;
@@ -100,7 +103,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
for (idx = 0; idx < (1UL << ptidxbits); idx++) {
pte_addr = base + idx * ptesize;
- cpu_physical_memory_read(pte_addr, &pte, ptesize);
+ address_space_read(as, pte_addr, attrs, &pte, ptesize);
paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
attr = pte & 0xff;
@@ -132,7 +135,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
*last_size = pgsize;
} else {
/* pointer to the next level of the page table */
- walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize,
+ walk_pte(mon, as, paddr, start, level - 1, ptidxbits, ptesize,
va_bits, vbase, pbase, last_paddr,
last_size, last_attr);
}
@@ -145,6 +148,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
static void mem_info_svxx(Monitor *mon, CPUArchState *env)
{
+ AddressSpace *as = env_cpu(env)->as;
int levels, ptidxbits, ptesize, vm, va_bits;
hwaddr base;
target_ulong vbase;
@@ -199,7 +203,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
last_attr = 0;
/* walk page tables, starting from address 0 */
- walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
+ walk_pte(mon, as, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
&vbase, &pbase, &last_paddr, &last_size, &last_attr);
/* don't forget the last one */
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 6fc06c7..9a53aec 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -286,7 +286,8 @@ static void exit_tb(DisasContext *ctx)
tcg_gen_exit_tb(NULL, 0);
}
-static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx,
+ target_long diff)
{
target_ulong dest = ctx->base.pc_next + diff;
@@ -305,12 +306,12 @@ static void gen_goto_tb(DisasContext *ctx, int n, target_long diff)
*/
if (tb_cflags(ctx->base.tb) & CF_PCREL) {
gen_update_pc(ctx, diff);
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(n);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_update_pc(ctx, diff);
}
- tcg_gen_exit_tb(ctx->base.tb, n);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_update_pc(ctx, diff);
lookup_and_goto_ptr(ctx);
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 41ea223..2de3358 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -235,26 +235,26 @@ vext_continuous_ldst_host(CPURISCVState *env, vext_ldst_elem_fn_host *ldst_host,
void *vd, uint32_t evl, uint32_t reg_start, void *host,
uint32_t esz, bool is_load)
{
-#if HOST_BIG_ENDIAN
- for (; reg_start < evl; reg_start++, host += esz) {
- ldst_host(vd, reg_start, host);
- }
-#else
- if (esz == 1) {
- uint32_t byte_offset = reg_start * esz;
- uint32_t size = (evl - reg_start) * esz;
-
- if (is_load) {
- memcpy(vd + byte_offset, host, size);
- } else {
- memcpy(host, vd + byte_offset, size);
- }
- } else {
+ if (HOST_BIG_ENDIAN) {
for (; reg_start < evl; reg_start++, host += esz) {
ldst_host(vd, reg_start, host);
}
+ } else {
+ if (esz == 1) {
+ uint32_t byte_offset = reg_start * esz;
+ uint32_t size = (evl - reg_start) * esz;
+
+ if (is_load) {
+ memcpy(vd + byte_offset, host, size);
+ } else {
+ memcpy(host, vd + byte_offset, size);
+ }
+ } else {
+ for (; reg_start < evl; reg_start++, host += esz) {
+ ldst_host(vd, reg_start, host);
+ }
+ }
}
-#endif
}
static void vext_set_tail_elems_1s(target_ulong vl, void *vd,
generated by cgit v1.1 at 2025-10-17 15:19:36 +0000