aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/translate.c
diff options
context:
space:
mode:
Diffstat (limited to 'target/riscv/translate.c')
-rw-r--r--target/riscv/translate.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e44254e..e356fc6 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -232,11 +232,6 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
g_assert_not_reached();
}
-static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
-{
- tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
-}
-
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || ctx->w) {
@@ -637,9 +632,11 @@ void riscv_translate_init(void)
{
int i;
- /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
- /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
- /* registers, unless you specifically block reads/writes to reg 0 */
+ /*
+ * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
+ * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
+ * unless you specifically block reads/writes to reg 0.
+ */
cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) {