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Diffstat (limited to 'target/riscv/insn_trans/trans_xventanacondops.c.inc')
-rw-r--r--target/riscv/insn_trans/trans_xventanacondops.c.inc18
1 files changed, 3 insertions, 15 deletions
diff --git a/target/riscv/insn_trans/trans_xventanacondops.c.inc b/target/riscv/insn_trans/trans_xventanacondops.c.inc
index 16849e6..38c15f2 100644
--- a/target/riscv/insn_trans/trans_xventanacondops.c.inc
+++ b/target/riscv/insn_trans/trans_xventanacondops.c.inc
@@ -1,7 +1,7 @@
/*
* RISC-V translation routines for the XVentanaCondOps extension.
*
- * Copyright (c) 2021-2022 VRULL GmbH.
+ * Copyright (c) 2021-2023 VRULL GmbH.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -16,24 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
-static bool gen_vt_condmask(DisasContext *ctx, arg_r *a, TCGCond cond)
-{
- TCGv dest = dest_gpr(ctx, a->rd);
- TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
- TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
-
- tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, ctx->zero);
-
- gen_set_gpr(ctx, a->rd, dest);
- return true;
-}
-
static bool trans_vt_maskc(DisasContext *ctx, arg_r *a)
{
- return gen_vt_condmask(ctx, a, TCG_COND_NE);
+ return gen_logic(ctx, a, gen_czero_eqz);
}
static bool trans_vt_maskcn(DisasContext *ctx, arg_r *a)
{
- return gen_vt_condmask(ctx, a, TCG_COND_EQ);
+ return gen_logic(ctx, a, gen_czero_nez);
}