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-rw-r--r--target/riscv/debug.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c79b51a..f6241a8 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -30,7 +30,7 @@
#include "trace.h"
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
-#include "sysemu/cpu-timers.h"
+#include "system/cpu-timers.h"
/*
* The following M-mode trigger CSRs are implemented: