aboutsummaryrefslogtreecommitdiff
path: root/target/riscv/cpu.h
diff options
context:
space:
mode:
Diffstat (limited to 'target/riscv/cpu.h')
-rw-r--r--target/riscv/cpu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2c22664..4c13012 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -50,7 +50,7 @@ typedef struct CPUArchState CPURISCVState;
*/
#define RISCV_UW2_ALWAYS_STORE_AMO 1
-#define RV(x) ((target_ulong)1 << (x - 'A'))
+#define RV(x) BIT(x - 'A')
/*
* Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[]
@@ -582,7 +582,7 @@ struct RISCVCPUClass {
RISCVCPUDef *def;
};
-static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
+static inline int riscv_has_ext(CPURISCVState *env, uint32_t ext)
{
return (env->misa_ext & ext) != 0;
}