diff options
Diffstat (limited to 'target/m68k/cpu.h')
| -rw-r--r-- | target/m68k/cpu.h | 29 |
1 files changed, 18 insertions, 11 deletions
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 5ef200a..20de3c3 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -106,9 +106,11 @@ typedef struct CPUM68KState { float_status fp_status; uint64_t mactmp; - /* EMAC Hardware deals with 48-bit values composed of one 32-bit and - two 8-bit parts. We store a single 64-bit value and - rearrange/extend this when changing modes. */ + /* + * EMAC Hardware deals with 48-bit values composed of one 32-bit and + * two 8-bit parts. We store a single 64-bit value and + * rearrange/extend this when changing modes. + */ uint64_t macc[4]; uint32_t macsr; uint32_t mac_mask; @@ -146,7 +148,7 @@ typedef struct CPUM68KState { uint32_t features; } CPUM68KState; -/** +/* * M68kCPU: * @env: #CPUM68KState * @@ -171,9 +173,11 @@ int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); -/* you can call this signal handler from your SIGBUS and SIGSEGV - signal handlers to inform the virtual CPU of exceptions. non zero - is returned if the signal was handled by the virtual CPU. */ +/* + * you can call this signal handler from your SIGBUS and SIGSEGV + * signal handlers to inform the virtual CPU of exceptions. non zero + * is returned if the signal was handled by the virtual CPU. + */ int cpu_m68k_signal_handler(int host_signum, void *pinfo, void *puc); uint32_t cpu_m68k_get_ccr(CPUM68KState *env); @@ -182,7 +186,8 @@ void cpu_m68k_set_sr(CPUM68KState *env, uint32_t); void cpu_m68k_set_fpcr(CPUM68KState *env, uint32_t val); -/* Instead of computing the condition codes after each m68k instruction, +/* + * Instead of computing the condition codes after each m68k instruction, * QEMU just stores one operand (called CC_SRC), the result * (called CC_DEST) and the type of operation (called CC_OP). When the * condition codes are needed, the condition codes can be calculated @@ -447,9 +452,11 @@ void m68k_switch_sp(CPUM68KState *env); void do_m68k_semihosting(CPUM68KState *env, int nr); -/* There are 4 ColdFire core ISA revisions: A, A+, B and C. - Each feature covers the subset of instructions common to the - ISA revisions mentioned. */ +/* + * There are 4 ColdFire core ISA revisions: A, A+, B and C. + * Each feature covers the subset of instructions common to the + * ISA revisions mentioned. + */ enum m68k_features { M68K_FEATURE_M68000, |