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-rw-r--r--target/alpha/cpu-param.h4
-rw-r--r--target/alpha/cpu.c37
-rw-r--r--target/alpha/cpu.h15
-rw-r--r--target/alpha/fpu_helper.c1
-rw-r--r--target/alpha/helper.c2
-rw-r--r--target/alpha/helper.h2
-rw-r--r--target/alpha/int_helper.c1
-rw-r--r--target/alpha/machine.c36
-rw-r--r--target/alpha/mem_helper.c3
-rw-r--r--target/alpha/sys_helper.c11
-rw-r--r--target/alpha/translate.c34
-rw-r--r--target/alpha/vax_helper.c1
12 files changed, 70 insertions, 77 deletions
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index ff06e41..a799f42 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -18,14 +18,12 @@
* a 4k minimum to match x86 host, which can minimize emulation issues.
*/
# define TARGET_PAGE_BITS_VARY
-# define TARGET_PAGE_BITS_MIN 12
# define TARGET_VIRT_ADDR_SPACE_BITS 63
#else
# define TARGET_PAGE_BITS 13
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
-/* Alpha processors have a weak memory model */
-#define TCG_GUEST_DEFAULT_MO (0)
+#define TARGET_INSN_START_EXTRA_WORDS 0
#endif
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
index 584c2aa..932cdda 100644
--- a/target/alpha/cpu.c
+++ b/target/alpha/cpu.c
@@ -23,8 +23,9 @@
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
-#include "exec/exec-all.h"
#include "exec/translation-block.h"
+#include "exec/target_page.h"
+#include "accel/tcg/cpu-ops.h"
#include "fpu/softfloat.h"
@@ -40,6 +41,18 @@ static vaddr alpha_cpu_get_pc(CPUState *cs)
return env->pc;
}
+static TCGTBCPUState alpha_get_tb_cpu_state(CPUState *cs)
+{
+ CPUAlphaState *env = cpu_env(cs);
+ uint32_t flags = env->flags & ENV_FLAG_TB_MASK;
+
+#ifdef CONFIG_USER_ONLY
+ flags |= TB_FLAG_UNALIGN * !cs->prctl_unalign_sigbus;
+#endif
+
+ return (TCGTBCPUState){ .pc = env->pc, .flags = flags };
+}
+
static void alpha_cpu_synchronize_from_tb(CPUState *cs,
const TranslationBlock *tb)
{
@@ -73,10 +86,10 @@ static bool alpha_cpu_has_work(CPUState *cs)
assume that if a CPU really wants to stay asleep, it will mask
interrupts at the chipset level, which will prevent these bits
from being set in the first place. */
- return cs->interrupt_request & (CPU_INTERRUPT_HARD
- | CPU_INTERRUPT_TIMER
- | CPU_INTERRUPT_SMP
- | CPU_INTERRUPT_MCHK);
+ return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD
+ | CPU_INTERRUPT_TIMER
+ | CPU_INTERRUPT_SMP
+ | CPU_INTERRUPT_MCHK);
}
#endif /* !CONFIG_USER_ONLY */
@@ -231,28 +244,34 @@ static const struct SysemuCPUOps alpha_sysemu_ops = {
};
#endif
-#include "accel/tcg/cpu-ops.h"
-
static const TCGCPUOps alpha_tcg_ops = {
+ /* Alpha processors have a weak memory model */
+ .guest_default_memory_order = 0,
+ .mttcg_supported = true,
+
.initialize = alpha_translate_init,
.translate_code = alpha_translate_code,
+ .get_tb_cpu_state = alpha_get_tb_cpu_state,
.synchronize_from_tb = alpha_cpu_synchronize_from_tb,
.restore_state_to_opc = alpha_restore_state_to_opc,
+ .mmu_index = alpha_cpu_mmu_index,
#ifdef CONFIG_USER_ONLY
.record_sigsegv = alpha_cpu_record_sigsegv,
.record_sigbus = alpha_cpu_record_sigbus,
#else
.tlb_fill = alpha_cpu_tlb_fill,
+ .pointer_wrap = cpu_pointer_wrap_notreached,
.cpu_exec_interrupt = alpha_cpu_exec_interrupt,
.cpu_exec_halt = alpha_cpu_has_work,
+ .cpu_exec_reset = cpu_reset,
.do_interrupt = alpha_cpu_do_interrupt,
.do_transaction_failed = alpha_cpu_do_transaction_failed,
.do_unaligned_access = alpha_cpu_do_unaligned_access,
#endif /* !CONFIG_USER_ONLY */
};
-static void alpha_cpu_class_init(ObjectClass *oc, void *data)
+static void alpha_cpu_class_init(ObjectClass *oc, const void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
@@ -262,12 +281,12 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
&acc->parent_realize);
cc->class_by_name = alpha_cpu_class_by_name;
- cc->mmu_index = alpha_cpu_mmu_index;
cc->dump_state = alpha_cpu_dump_state;
cc->set_pc = alpha_cpu_set_pc;
cc->get_pc = alpha_cpu_get_pc;
cc->gdb_read_register = alpha_cpu_gdb_read_register;
cc->gdb_write_register = alpha_cpu_gdb_write_register;
+ cc->gdb_core_xml_file = "alpha-core.xml";
#ifndef CONFIG_USER_ONLY
dc->vmsd = &vmstate_alpha_cpu;
cc->sysemu_ops = &alpha_sysemu_ops;
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 80562ad..45944e4 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -21,7 +21,9 @@
#define ALPHA_CPU_H
#include "cpu-qom.h"
+#include "exec/cpu-common.h"
#include "exec/cpu-defs.h"
+#include "exec/cpu-interrupt.h"
#include "qemu/cpu-float.h"
#define ICACHE_LINE_SIZE 32
@@ -287,8 +289,6 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, int flags);
int alpha_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
-#include "exec/cpu-all.h"
-
enum {
FEATURE_ASN = 0x00000001,
FEATURE_SPS = 0x00000002,
@@ -464,17 +464,6 @@ void alpha_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
MemTxResult response, uintptr_t retaddr);
#endif
-static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, vaddr *pc,
- uint64_t *cs_base, uint32_t *pflags)
-{
- *pc = env->pc;
- *cs_base = 0;
- *pflags = env->flags & ENV_FLAG_TB_MASK;
-#ifdef CONFIG_USER_ONLY
- *pflags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
-#endif
-}
-
#ifdef CONFIG_USER_ONLY
/* Copied from linux ieee_swcr_to_fpcr. */
static inline uint64_t alpha_ieee_swcr_to_fpcr(uint64_t swcr)
diff --git a/target/alpha/fpu_helper.c b/target/alpha/fpu_helper.c
index 6aefb9b..30f3c7f 100644
--- a/target/alpha/fpu_helper.c
+++ b/target/alpha/fpu_helper.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
diff --git a/target/alpha/helper.c b/target/alpha/helper.c
index 57cefcb..096eac3 100644
--- a/target/alpha/helper.c
+++ b/target/alpha/helper.c
@@ -22,9 +22,11 @@
#include "cpu.h"
#include "exec/cputlb.h"
#include "exec/page-protection.h"
+#include "exec/target_page.h"
#include "fpu/softfloat-types.h"
#include "exec/helper-proto.h"
#include "qemu/qemu-print.h"
+#include "system/memory.h"
#define CONVERT_BIT(X, SRC, DST) \
diff --git a/target/alpha/helper.h b/target/alpha/helper.h
index d60f208..954a5c8 100644
--- a/target/alpha/helper.h
+++ b/target/alpha/helper.h
@@ -90,9 +90,9 @@ DEF_HELPER_FLAGS_2(ieee_input_s, TCG_CALL_NO_WG, void, env, i64)
#if !defined (CONFIG_USER_ONLY)
DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64)
-DEF_HELPER_FLAGS_1(tb_flush, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_1(halt, void, i64)
+DEF_HELPER_1(whami, i64, env)
DEF_HELPER_FLAGS_0(get_vmtime, TCG_CALL_NO_RWG, i64)
DEF_HELPER_FLAGS_0(get_walltime, TCG_CALL_NO_RWG, i64)
diff --git a/target/alpha/int_helper.c b/target/alpha/int_helper.c
index 5672696..6bfe635 100644
--- a/target/alpha/int_helper.c
+++ b/target/alpha/int_helper.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "qemu/host-utils.h"
diff --git a/target/alpha/machine.c b/target/alpha/machine.c
index f09834f..6828b12 100644
--- a/target/alpha/machine.c
+++ b/target/alpha/machine.c
@@ -25,8 +25,8 @@ static const VMStateInfo vmstate_fpcr = {
};
static const VMStateField vmstate_env_fields[] = {
- VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31),
- VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31),
+ VMSTATE_UINT64_ARRAY(ir, CPUAlphaState, 31),
+ VMSTATE_UINT64_ARRAY(fir, CPUAlphaState, 31),
/* Save the architecture value of the fpcr, not the internally
expanded version. Since this architecture value does not
exist in memory to be stored, this requires a but of hoop
@@ -41,27 +41,27 @@ static const VMStateField vmstate_env_fields[] = {
.flags = VMS_SINGLE,
.offset = 0
},
- VMSTATE_UINTTL(pc, CPUAlphaState),
- VMSTATE_UINTTL(unique, CPUAlphaState),
- VMSTATE_UINTTL(lock_addr, CPUAlphaState),
- VMSTATE_UINTTL(lock_value, CPUAlphaState),
+ VMSTATE_UINT64(pc, CPUAlphaState),
+ VMSTATE_UINT64(unique, CPUAlphaState),
+ VMSTATE_UINT64(lock_addr, CPUAlphaState),
+ VMSTATE_UINT64(lock_value, CPUAlphaState),
VMSTATE_UINT32(flags, CPUAlphaState),
VMSTATE_UINT32(pcc_ofs, CPUAlphaState),
- VMSTATE_UINTTL(trap_arg0, CPUAlphaState),
- VMSTATE_UINTTL(trap_arg1, CPUAlphaState),
- VMSTATE_UINTTL(trap_arg2, CPUAlphaState),
+ VMSTATE_UINT64(trap_arg0, CPUAlphaState),
+ VMSTATE_UINT64(trap_arg1, CPUAlphaState),
+ VMSTATE_UINT64(trap_arg2, CPUAlphaState),
- VMSTATE_UINTTL(exc_addr, CPUAlphaState),
- VMSTATE_UINTTL(palbr, CPUAlphaState),
- VMSTATE_UINTTL(ptbr, CPUAlphaState),
- VMSTATE_UINTTL(vptptr, CPUAlphaState),
- VMSTATE_UINTTL(sysval, CPUAlphaState),
- VMSTATE_UINTTL(usp, CPUAlphaState),
+ VMSTATE_UINT64(exc_addr, CPUAlphaState),
+ VMSTATE_UINT64(palbr, CPUAlphaState),
+ VMSTATE_UINT64(ptbr, CPUAlphaState),
+ VMSTATE_UINT64(vptptr, CPUAlphaState),
+ VMSTATE_UINT64(sysval, CPUAlphaState),
+ VMSTATE_UINT64(usp, CPUAlphaState),
- VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8),
- VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24),
+ VMSTATE_UINT64_ARRAY(shadow, CPUAlphaState, 8),
+ VMSTATE_UINT64_ARRAY(scratch, CPUAlphaState, 24),
VMSTATE_END_OF_LIST()
};
@@ -74,7 +74,7 @@ static const VMStateDescription vmstate_env = {
};
static const VMStateField vmstate_cpu_fields[] = {
- VMSTATE_CPU(),
+ VMSTATE_STRUCT(parent_obj, AlphaCPU, 0, vmstate_cpu_common, CPUState),
VMSTATE_STRUCT(env, AlphaCPU, 1, vmstate_env, CPUAlphaState),
VMSTATE_END_OF_LIST()
};
diff --git a/target/alpha/mem_helper.c b/target/alpha/mem_helper.c
index 872955f..2113fe3 100644
--- a/target/alpha/mem_helper.c
+++ b/target/alpha/mem_helper.c
@@ -20,8 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
-#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
+#include "accel/tcg/cpu-ldst.h"
static void do_unaligned_access(CPUAlphaState *env, vaddr addr, uintptr_t retaddr)
{
diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c
index 51e3254..0e0a619 100644
--- a/target/alpha/sys_helper.c
+++ b/target/alpha/sys_helper.c
@@ -20,7 +20,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/cputlb.h"
-#include "exec/tb-flush.h"
#include "exec/helper-proto.h"
#include "system/runstate.h"
#include "system/system.h"
@@ -38,11 +37,6 @@ void helper_tbis(CPUAlphaState *env, uint64_t p)
tlb_flush_page(env_cpu(env), p);
}
-void helper_tb_flush(CPUAlphaState *env)
-{
- tb_flush(env_cpu(env));
-}
-
void helper_halt(uint64_t restart)
{
if (restart) {
@@ -73,3 +67,8 @@ void helper_set_alarm(CPUAlphaState *env, uint64_t expire)
timer_del(cpu->alarm_timer);
}
}
+
+uint64_t HELPER(whami)(CPUAlphaState *env)
+{
+ return env_cpu(env)->cpu_index;
+}
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 2156c02..b1d8a4e 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -21,12 +21,12 @@
#include "cpu.h"
#include "system/cpus.h"
#include "qemu/host-utils.h"
-#include "exec/exec-all.h"
#include "tcg/tcg-op.h"
#include "exec/helper-proto.h"
#include "exec/helper-gen.h"
#include "exec/translator.h"
#include "exec/translation-block.h"
+#include "exec/target_page.h"
#include "exec/log.h"
#define HELPER_H "helper.h"
@@ -48,8 +48,6 @@ struct DisasContext {
#ifdef CONFIG_USER_ONLY
MemOp unalign;
-#else
- uint64_t palbr;
#endif
uint32_t tbflags;
int mem_idx;
@@ -438,18 +436,18 @@ static DisasJumpType gen_store_conditional(DisasContext *ctx, int ra, int rb,
return DISAS_NEXT;
}
-static void gen_goto_tb(DisasContext *ctx, int idx, int32_t disp)
+static void gen_goto_tb(DisasContext *ctx, unsigned tb_slot_idx, int32_t disp)
{
if (translator_use_goto_tb(&ctx->base, ctx->base.pc_next + disp)) {
/* With PCREL, PC must always be up-to-date. */
if (ctx->pcrel) {
gen_pc_disp(ctx, cpu_pc, disp);
- tcg_gen_goto_tb(idx);
+ tcg_gen_goto_tb(tb_slot_idx);
} else {
- tcg_gen_goto_tb(idx);
+ tcg_gen_goto_tb(tb_slot_idx);
gen_pc_disp(ctx, cpu_pc, disp);
}
- tcg_gen_exit_tb(ctx->base.tb, idx);
+ tcg_gen_exit_tb(ctx->base.tb, tb_slot_idx);
} else {
gen_pc_disp(ctx, cpu_pc, disp);
tcg_gen_lookup_and_goto_ptr();
@@ -1128,8 +1126,7 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
break;
case 0x3C:
/* WHAMI */
- tcg_gen_ld32s_i64(ctx->ir[IR_V0], tcg_env,
- -offsetof(AlphaCPU, env) + offsetof(CPUState, cpu_index));
+ gen_helper_whami(ctx->ir[IR_V0], tcg_env);
break;
case 0x3E:
@@ -1155,7 +1152,6 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
#else
{
TCGv tmp = tcg_temp_new();
- uint64_t entry;
gen_pc_disp(ctx, tmp, 0);
if (ctx->tbflags & ENV_FLAG_PAL_MODE) {
@@ -1165,12 +1161,11 @@ static DisasJumpType gen_call_pal(DisasContext *ctx, int palcode)
}
tcg_gen_st_i64(tmp, tcg_env, offsetof(CPUAlphaState, exc_addr));
- entry = ctx->palbr;
- entry += (palcode & 0x80
- ? 0x2000 + (palcode - 0x80) * 64
- : 0x1000 + palcode * 64);
-
- tcg_gen_movi_i64(cpu_pc, entry);
+ tcg_gen_ld_i64(cpu_pc, tcg_env, offsetof(CPUAlphaState, palbr));
+ tcg_gen_addi_i64(cpu_pc, cpu_pc,
+ palcode & 0x80
+ ? 0x2000 + (palcode - 0x80) * 64
+ : 0x1000 + palcode * 64);
return DISAS_PC_UPDATED;
}
#endif
@@ -1292,11 +1287,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno)
case 7:
/* PALBR */
tcg_gen_st_i64(vb, tcg_env, offsetof(CPUAlphaState, palbr));
- /* Changing the PAL base register implies un-chaining all of the TBs
- that ended with a CALL_PAL. Since the base register usually only
- changes during boot, flushing everything works well. */
- gen_helper_tb_flush(tcg_env);
- return DISAS_PC_STALE;
+ break;
case 32 ... 39:
/* Accessing the "non-shadow" general registers. */
@@ -2874,7 +2865,6 @@ static void alpha_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
ctx->ir = cpu_std_ir;
ctx->unalign = (ctx->tbflags & TB_FLAG_UNALIGN ? MO_UNALN : MO_ALIGN);
#else
- ctx->palbr = env->palbr;
ctx->ir = (ctx->tbflags & ENV_FLAG_PAL_MODE ? cpu_pal_ir : cpu_std_ir);
#endif
diff --git a/target/alpha/vax_helper.c b/target/alpha/vax_helper.c
index f94fb51..c1d201e 100644
--- a/target/alpha/vax_helper.c
+++ b/target/alpha/vax_helper.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
generated by cgit v1.1 at 2025-10-17 16:59:19 +0000