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-rw-r--r--include/hw/ppc/xive_regs.h32
1 files changed, 16 insertions, 16 deletions
diff --git a/include/hw/ppc/xive_regs.h b/include/hw/ppc/xive_regs.h
index b9db7ab..9d52d46 100644
--- a/include/hw/ppc/xive_regs.h
+++ b/include/hw/ppc/xive_regs.h
@@ -114,23 +114,23 @@
* Then we have all these "special" CI ops at these offset that trigger
* all sorts of side effects:
*/
-#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
-#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
+#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg */
+#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
-#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
- * context */
-#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
-#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
- * context to reg */
-#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
- * context to reg*/
-#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
-#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
- * line */
-#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
-#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
- * line */
-#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
+#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user */
+ /* context */
+#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
+#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS */
+ /* context to reg */
+#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool */
+ /* context to reg */
+#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
+#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd */
+ /* line */
+#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
+#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even */
+ /* line */
+#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
/* XXX more... */
/* NSR fields for the various QW ack types */