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-rw-r--r--hw/arm/fsl-imx25.c6
-rw-r--r--hw/arm/fsl-imx6.c6
-rw-r--r--hw/arm/fsl-imx6ul.c2
-rw-r--r--hw/arm/fsl-imx7.c2
-rw-r--r--hw/misc/imx6ul_ccm.c76
-rw-r--r--hw/net/ftgmac100.c26
-rw-r--r--hw/net/imx_fec.c106
-rw-r--r--hw/net/trace-events18
-rw-r--r--hw/sd/sdhci-internal.h5
-rw-r--r--hw/sd/sdhci.c18
10 files changed, 188 insertions, 77 deletions
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index fb516bd..f32f9bc 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -263,6 +263,12 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp)
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABILITIES,
"capareg", &err);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
+ "vendor", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 1759348..d4bc4fa 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -339,6 +339,12 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp)
&err);
object_property_set_uint(OBJECT(&s->esdhc[i]), IMX6_ESDHC_CAPABILITIES,
"capareg", &err);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), SDHCI_VENDOR_IMX,
+ "vendor", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
sysbus_realize(SYS_BUS_DEVICE(&s->esdhc[i]), &err);
if (err) {
error_propagate(errp, err);
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index f8c5640..6446034 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -479,6 +479,8 @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
FSL_IMX6UL_USDHC2_IRQ,
};
+ object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX,
+ "vendor", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index ca8b5cc..b49d895 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -393,6 +393,8 @@ static void fsl_imx7_realize(DeviceState *dev, Error **errp)
FSL_IMX7_USDHC3_IRQ,
};
+ object_property_set_uint(OBJECT(&s->usdhc[i]), SDHCI_VENDOR_IMX,
+ "vendor", &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->usdhc[i]), &error_abort);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->usdhc[i]), 0,
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
index a2fc1d0..5e0661d 100644
--- a/hw/misc/imx6ul_ccm.c
+++ b/hw/misc/imx6ul_ccm.c
@@ -19,6 +19,62 @@
#include "trace.h"
+static const uint32_t ccm_mask[CCM_MAX] = {
+ [CCM_CCR] = 0xf01fef80,
+ [CCM_CCDR] = 0xfffeffff,
+ [CCM_CSR] = 0xffffffff,
+ [CCM_CCSR] = 0xfffffef2,
+ [CCM_CACRR] = 0xfffffff8,
+ [CCM_CBCDR] = 0xc1f8e000,
+ [CCM_CBCMR] = 0xfc03cfff,
+ [CCM_CSCMR1] = 0x80700000,
+ [CCM_CSCMR2] = 0xe01ff003,
+ [CCM_CSCDR1] = 0xfe00c780,
+ [CCM_CS1CDR] = 0xfe00fe00,
+ [CCM_CS2CDR] = 0xf8007000,
+ [CCM_CDCDR] = 0xf00fffff,
+ [CCM_CHSCCDR] = 0xfffc01ff,
+ [CCM_CSCDR2] = 0xfe0001ff,
+ [CCM_CSCDR3] = 0xffffc1ff,
+ [CCM_CDHIPR] = 0xffffffff,
+ [CCM_CTOR] = 0x00000000,
+ [CCM_CLPCR] = 0xf39ff01c,
+ [CCM_CISR] = 0xfb85ffbe,
+ [CCM_CIMR] = 0xfb85ffbf,
+ [CCM_CCOSR] = 0xfe00fe00,
+ [CCM_CGPR] = 0xfffc3fea,
+ [CCM_CCGR0] = 0x00000000,
+ [CCM_CCGR1] = 0x00000000,
+ [CCM_CCGR2] = 0x00000000,
+ [CCM_CCGR3] = 0x00000000,
+ [CCM_CCGR4] = 0x00000000,
+ [CCM_CCGR5] = 0x00000000,
+ [CCM_CCGR6] = 0x00000000,
+ [CCM_CMEOR] = 0xafffff1f,
+};
+
+static const uint32_t analog_mask[CCM_ANALOG_MAX] = {
+ [CCM_ANALOG_PLL_ARM] = 0xfff60f80,
+ [CCM_ANALOG_PLL_USB1] = 0xfffe0fbc,
+ [CCM_ANALOG_PLL_USB2] = 0xfffe0fbc,
+ [CCM_ANALOG_PLL_SYS] = 0xfffa0ffe,
+ [CCM_ANALOG_PLL_SYS_SS] = 0x00000000,
+ [CCM_ANALOG_PLL_SYS_NUM] = 0xc0000000,
+ [CCM_ANALOG_PLL_SYS_DENOM] = 0xc0000000,
+ [CCM_ANALOG_PLL_AUDIO] = 0xffe20f80,
+ [CCM_ANALOG_PLL_AUDIO_NUM] = 0xc0000000,
+ [CCM_ANALOG_PLL_AUDIO_DENOM] = 0xc0000000,
+ [CCM_ANALOG_PLL_VIDEO] = 0xffe20f80,
+ [CCM_ANALOG_PLL_VIDEO_NUM] = 0xc0000000,
+ [CCM_ANALOG_PLL_VIDEO_DENOM] = 0xc0000000,
+ [CCM_ANALOG_PLL_ENET] = 0xffc20ff0,
+ [CCM_ANALOG_PFD_480] = 0x40404040,
+ [CCM_ANALOG_PFD_528] = 0x40404040,
+ [PMU_MISC0] = 0x01fe8306,
+ [PMU_MISC1] = 0x07fcede0,
+ [PMU_MISC2] = 0x005f5f5f,
+};
+
static const char *imx6ul_ccm_reg_name(uint32_t reg)
{
static char unknown[20];
@@ -596,11 +652,8 @@ static void imx6ul_ccm_write(void *opaque, hwaddr offset, uint64_t value,
trace_ccm_write_reg(imx6ul_ccm_reg_name(index), (uint32_t)value);
- /*
- * We will do a better implementation later. In particular some bits
- * cannot be written to.
- */
- s->ccm[index] = (uint32_t)value;
+ s->ccm[index] = (s->ccm[index] & ccm_mask[index]) |
+ ((uint32_t)value & ~ccm_mask[index]);
}
static uint64_t imx6ul_analog_read(void *opaque, hwaddr offset, unsigned size)
@@ -737,7 +790,7 @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
* the REG_NAME register. So we change the value of the
* REG_NAME register, setting bits passed in the value.
*/
- s->analog[index - 1] |= value;
+ s->analog[index - 1] |= (value & ~analog_mask[index - 1]);
break;
case CCM_ANALOG_PLL_ARM_CLR:
case CCM_ANALOG_PLL_USB1_CLR:
@@ -762,7 +815,7 @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
* the REG_NAME register. So we change the value of the
* REG_NAME register, unsetting bits passed in the value.
*/
- s->analog[index - 2] &= ~value;
+ s->analog[index - 2] &= ~(value & ~analog_mask[index - 2]);
break;
case CCM_ANALOG_PLL_ARM_TOG:
case CCM_ANALOG_PLL_USB1_TOG:
@@ -787,14 +840,11 @@ static void imx6ul_analog_write(void *opaque, hwaddr offset, uint64_t value,
* the REG_NAME register. So we change the value of the
* REG_NAME register, toggling bits passed in the value.
*/
- s->analog[index - 3] ^= value;
+ s->analog[index - 3] ^= (value & ~analog_mask[index - 3]);
break;
default:
- /*
- * We will do a better implementation later. In particular some bits
- * cannot be written to.
- */
- s->analog[index] = value;
+ s->analog[index] = (s->analog[index] & analog_mask[index]) |
+ (value & ~analog_mask[index]);
break;
}
}
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
index 25ebee7..043ba61 100644
--- a/hw/net/ftgmac100.c
+++ b/hw/net/ftgmac100.c
@@ -80,6 +80,16 @@
#define FTGMAC100_APTC_TXPOLL_TIME_SEL (1 << 12)
/*
+ * DMA burst length and arbitration control register
+ */
+#define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) >> 8) & 0x3)
+#define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) >> 10) & 0x3)
+#define FTGMAC100_DBLAC_RXDES_SIZE(x) ((((x) >> 12) & 0xf) * 8)
+#define FTGMAC100_DBLAC_TXDES_SIZE(x) ((((x) >> 16) & 0xf) * 8)
+#define FTGMAC100_DBLAC_IFG_CNT(x) (((x) >> 20) & 0x7)
+#define FTGMAC100_DBLAC_IFG_INC (1 << 23)
+
+/*
* PHY control register
*/
#define FTGMAC100_PHYCR_MIIRD (1 << 26)
@@ -553,7 +563,7 @@ static void ftgmac100_do_tx(FTGMAC100State *s, uint32_t tx_ring,
if (bd.des0 & s->txdes0_edotr) {
addr = tx_ring;
} else {
- addr += sizeof(FTGMAC100Desc);
+ addr += FTGMAC100_DBLAC_TXDES_SIZE(s->dblac);
}
}
@@ -800,6 +810,18 @@ static void ftgmac100_write(void *opaque, hwaddr addr,
s->phydata = value & 0xffff;
break;
case FTGMAC100_DBLAC: /* DMA Burst Length and Arbitration Control */
+ if (FTGMAC100_DBLAC_TXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: transmit descriptor too small : %d bytes\n",
+ __func__, FTGMAC100_DBLAC_TXDES_SIZE(s->dblac));
+ break;
+ }
+ if (FTGMAC100_DBLAC_RXDES_SIZE(s->dblac) < sizeof(FTGMAC100Desc)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: receive descriptor too small : %d bytes\n",
+ __func__, FTGMAC100_DBLAC_RXDES_SIZE(s->dblac));
+ break;
+ }
s->dblac = value;
break;
case FTGMAC100_REVR: /* Feature Register */
@@ -982,7 +1004,7 @@ static ssize_t ftgmac100_receive(NetClientState *nc, const uint8_t *buf,
if (bd.des0 & s->rxdes0_edorr) {
addr = s->rx_ring;
} else {
- addr += sizeof(FTGMAC100Desc);
+ addr += FTGMAC100_DBLAC_RXDES_SIZE(s->dblac);
}
}
s->rx_descriptor = addr;
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 7adcc9d..eefedc2 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -31,34 +31,11 @@
#include "qemu/module.h"
#include "net/checksum.h"
#include "net/eth.h"
+#include "trace.h"
/* For crc32 */
#include <zlib.h>
-#ifndef DEBUG_IMX_FEC
-#define DEBUG_IMX_FEC 0
-#endif
-
-#define FEC_PRINTF(fmt, args...) \
- do { \
- if (DEBUG_IMX_FEC) { \
- fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_FEC, \
- __func__, ##args); \
- } \
- } while (0)
-
-#ifndef DEBUG_IMX_PHY
-#define DEBUG_IMX_PHY 0
-#endif
-
-#define PHY_PRINTF(fmt, args...) \
- do { \
- if (DEBUG_IMX_PHY) { \
- fprintf(stderr, "[%s.phy]%s: " fmt , TYPE_IMX_FEC, \
- __func__, ##args); \
- } \
- } while (0)
-
#define IMX_MAX_DESC 1024
static const char *imx_default_reg_name(IMXFECState *s, uint32_t index)
@@ -262,43 +239,45 @@ static void imx_eth_update(IMXFECState *s);
* For now we don't handle any GPIO/interrupt line, so the OS will
* have to poll for the PHY status.
*/
-static void phy_update_irq(IMXFECState *s)
+static void imx_phy_update_irq(IMXFECState *s)
{
imx_eth_update(s);
}
-static void phy_update_link(IMXFECState *s)
+static void imx_phy_update_link(IMXFECState *s)
{
/* Autonegotiation status mirrors link status. */
if (qemu_get_queue(s->nic)->link_down) {
- PHY_PRINTF("link is down\n");
+ trace_imx_phy_update_link("down");
s->phy_status &= ~0x0024;
s->phy_int |= PHY_INT_DOWN;
} else {
- PHY_PRINTF("link is up\n");
+ trace_imx_phy_update_link("up");
s->phy_status |= 0x0024;
s->phy_int |= PHY_INT_ENERGYON;
s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
}
- phy_update_irq(s);
+ imx_phy_update_irq(s);
}
static void imx_eth_set_link(NetClientState *nc)
{
- phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
+ imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
}
-static void phy_reset(IMXFECState *s)
+static void imx_phy_reset(IMXFECState *s)
{
+ trace_imx_phy_reset();
+
s->phy_status = 0x7809;
s->phy_control = 0x3000;
s->phy_advertise = 0x01e1;
s->phy_int_mask = 0;
s->phy_int = 0;
- phy_update_link(s);
+ imx_phy_update_link(s);
}
-static uint32_t do_phy_read(IMXFECState *s, int reg)
+static uint32_t imx_phy_read(IMXFECState *s, int reg)
{
uint32_t val;
@@ -332,7 +311,7 @@ static uint32_t do_phy_read(IMXFECState *s, int reg)
case 29: /* Interrupt source. */
val = s->phy_int;
s->phy_int = 0;
- phy_update_irq(s);
+ imx_phy_update_irq(s);
break;
case 30: /* Interrupt mask */
val = s->phy_int_mask;
@@ -352,14 +331,14 @@ static uint32_t do_phy_read(IMXFECState *s, int reg)
break;
}
- PHY_PRINTF("read 0x%04x @ %d\n", val, reg);
+ trace_imx_phy_read(val, reg);
return val;
}
-static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
+static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
{
- PHY_PRINTF("write 0x%04x @ %d\n", val, reg);
+ trace_imx_phy_write(val, reg);
if (reg > 31) {
/* we only advertise one phy */
@@ -369,7 +348,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
switch (reg) {
case 0: /* Basic Control */
if (val & 0x8000) {
- phy_reset(s);
+ imx_phy_reset(s);
} else {
s->phy_control = val & 0x7980;
/* Complete autonegotiation immediately. */
@@ -383,7 +362,7 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
break;
case 30: /* Interrupt mask */
s->phy_int_mask = val & 0xff;
- phy_update_irq(s);
+ imx_phy_update_irq(s);
break;
case 17:
case 18:
@@ -402,6 +381,8 @@ static void do_phy_write(IMXFECState *s, int reg, uint32_t val)
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
{
dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
+
+ trace_imx_fec_read_bd(addr, bd->flags, bd->length, bd->data);
}
static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
@@ -412,6 +393,9 @@ static void imx_fec_write_bd(IMXFECBufDesc *bd, dma_addr_t addr)
static void imx_enet_read_bd(IMXENETBufDesc *bd, dma_addr_t addr)
{
dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd));
+
+ trace_imx_enet_read_bd(addr, bd->flags, bd->length, bd->data,
+ bd->option, bd->status);
}
static void imx_enet_write_bd(IMXENETBufDesc *bd, dma_addr_t addr)
@@ -471,11 +455,11 @@ static void imx_fec_do_tx(IMXFECState *s)
int len;
imx_fec_read_bd(&bd, addr);
- FEC_PRINTF("tx_bd %x flags %04x len %d data %08x\n",
- addr, bd.flags, bd.length, bd.data);
if ((bd.flags & ENET_BD_R) == 0) {
+
/* Run out of descriptors to transmit. */
- FEC_PRINTF("tx_bd ran out of descriptors to transmit\n");
+ trace_imx_eth_tx_bd_busy();
+
break;
}
len = bd.length;
@@ -552,11 +536,11 @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
int len;
imx_enet_read_bd(&bd, addr);
- FEC_PRINTF("tx_bd %x flags %04x len %d data %08x option %04x "
- "status %04x\n", addr, bd.flags, bd.length, bd.data,
- bd.option, bd.status);
if ((bd.flags & ENET_BD_R) == 0) {
/* Run out of descriptors to transmit. */
+
+ trace_imx_eth_tx_bd_busy();
+
break;
}
len = bd.length;
@@ -633,7 +617,7 @@ static void imx_eth_enable_rx(IMXFECState *s, bool flush)
s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0;
if (!s->regs[ENET_RDAR]) {
- FEC_PRINTF("RX buffer full\n");
+ trace_imx_eth_rx_bd_full();
} else if (flush) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
@@ -676,7 +660,7 @@ static void imx_eth_reset(DeviceState *d)
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
/* We also reset the PHY */
- phy_reset(s);
+ imx_phy_reset(s);
}
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
@@ -774,8 +758,7 @@ static uint64_t imx_eth_read(void *opaque, hwaddr offset, unsigned size)
break;
}
- FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
- value);
+ trace_imx_eth_read(index, imx_eth_reg_name(s, index), value);
return value;
}
@@ -884,8 +867,7 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
const bool single_tx_ring = !imx_eth_is_multi_tx_ring(s);
uint32_t index = offset >> 2;
- FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_eth_reg_name(s, index),
- (uint32_t)value);
+ trace_imx_eth_write(index, imx_eth_reg_name(s, index), value);
switch (index) {
case ENET_EIR:
@@ -940,12 +922,12 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
if (extract32(value, 29, 1)) {
/* This is a read operation */
s->regs[ENET_MMFR] = deposit32(s->regs[ENET_MMFR], 0, 16,
- do_phy_read(s,
+ imx_phy_read(s,
extract32(value,
18, 10)));
} else {
/* This a write operation */
- do_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
+ imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
}
/* raise the interrupt as the PHY operation is done */
s->regs[ENET_EIR] |= ENET_INT_MII;
@@ -1053,8 +1035,6 @@ static bool imx_eth_can_receive(NetClientState *nc)
{
IMXFECState *s = IMX_FEC(qemu_get_nic_opaque(nc));
- FEC_PRINTF("\n");
-
return !!s->regs[ENET_RDAR];
}
@@ -1071,7 +1051,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
unsigned int buf_len;
size_t size = len;
- FEC_PRINTF("len %d\n", (int)size);
+ trace_imx_fec_receive(size);
if (!s->regs[ENET_RDAR]) {
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n",
@@ -1113,7 +1093,7 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
bd.length = buf_len;
size -= buf_len;
- FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length);
+ trace_imx_fec_receive_len(addr, bd.length);
/* The last 4 bytes are the CRC. */
if (size < 4) {
@@ -1131,7 +1111,9 @@ static ssize_t imx_fec_receive(NetClientState *nc, const uint8_t *buf,
if (size == 0) {
/* Last buffer in frame. */
bd.flags |= flags | ENET_BD_L;
- FEC_PRINTF("rx frame flags %04x\n", bd.flags);
+
+ trace_imx_fec_receive_last(bd.flags);
+
s->regs[ENET_EIR] |= ENET_INT_RXF;
} else {
s->regs[ENET_EIR] |= ENET_INT_RXB;
@@ -1164,7 +1146,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
size_t size = len;
bool shift16 = s->regs[ENET_RACC] & ENET_RACC_SHIFT16;
- FEC_PRINTF("len %d\n", (int)size);
+ trace_imx_enet_receive(size);
if (!s->regs[ENET_RDAR]) {
qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Unexpected packet\n",
@@ -1210,7 +1192,7 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
bd.length = buf_len;
size -= buf_len;
- FEC_PRINTF("rx_bd 0x%x length %d\n", addr, bd.length);
+ trace_imx_enet_receive_len(addr, bd.length);
/* The last 4 bytes are the CRC. */
if (size < 4) {
@@ -1246,7 +1228,9 @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
if (size == 0) {
/* Last buffer in frame. */
bd.flags |= flags | ENET_BD_L;
- FEC_PRINTF("rx frame flags %04x\n", bd.flags);
+
+ trace_imx_enet_receive_last(bd.flags);
+
/* Indicate that we've updated the last buffer descriptor. */
bd.last_buffer = ENET_BD_BDU;
if (bd.option & ENET_BD_RX_INT) {
diff --git a/hw/net/trace-events b/hw/net/trace-events
index e18f883..26700da 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -408,3 +408,21 @@ i82596_receive_packet(size_t sz) "len=%zu"
i82596_new_mac(const char *id_with_mac) "New MAC for: %s"
i82596_set_multicast(uint16_t count) "Added %d multicast entries"
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
+
+# imx_fec.c
+imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
+imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
+imx_phy_update_link(const char *s) "%s"
+imx_phy_reset(void) ""
+imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
+imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
+imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
+imx_eth_rx_bd_full(void) "RX buffer is full"
+imx_eth_read(int reg, const char *reg_name, uint32_t value) "reg[%d:%s] => 0x%08"PRIx32
+imx_eth_write(int reg, const char *reg_name, uint64_t value) "reg[%d:%s] <= 0x%08"PRIx64
+imx_fec_receive(size_t size) "len %zu"
+imx_fec_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d"
+imx_fec_receive_last(int last) "rx frame flags 0x%04x"
+imx_enet_receive(size_t size) "len %zu"
+imx_enet_receive_len(uint64_t addr, int len) "rx_bd 0x%"PRIx64" length %d"
+imx_enet_receive_last(int last) "rx frame flags 0x%04x"
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index e7c8a52..e8c753d 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -75,6 +75,7 @@
#define SDHC_CMD_INHIBIT 0x00000001
#define SDHC_DATA_INHIBIT 0x00000002
#define SDHC_DAT_LINE_ACTIVE 0x00000004
+#define SDHC_IMX_CLOCK_GATE_OFF 0x00000080
#define SDHC_DOING_WRITE 0x00000100
#define SDHC_DOING_READ 0x00000200
#define SDHC_SPACE_AVAILABLE 0x00000400
@@ -289,7 +290,10 @@ extern const VMStateDescription sdhci_vmstate;
#define ESDHC_MIX_CTRL 0x48
+
#define ESDHC_VENDOR_SPEC 0xc0
+#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8)
+
#define ESDHC_DLL_CTRL 0x60
#define ESDHC_TUNING_CTRL 0xcc
@@ -326,6 +330,7 @@ extern const VMStateDescription sdhci_vmstate;
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \
+ DEFINE_PROP_UINT8("vendor", _state, vendor, SDHCI_VENDOR_NONE), \
\
/* Capabilities registers provide information on supported
* features of this specific host controller implementation */ \
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 1b75d7b..eb2be65 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1569,11 +1569,13 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
}
break;
+ case ESDHC_VENDOR_SPEC:
+ ret = s->vendor_spec;
+ break;
case ESDHC_DLL_CTRL:
case ESDHC_TUNE_CTRL_STATUS:
case ESDHC_UNDOCUMENTED_REG27:
case ESDHC_TUNING_CTRL:
- case ESDHC_VENDOR_SPEC:
case ESDHC_MIX_CTRL:
case ESDHC_WTMK_LVL:
ret = 0;
@@ -1596,7 +1598,21 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
case ESDHC_UNDOCUMENTED_REG27:
case ESDHC_TUNING_CTRL:
case ESDHC_WTMK_LVL:
+ break;
+
case ESDHC_VENDOR_SPEC:
+ s->vendor_spec = value;
+ switch (s->vendor) {
+ case SDHCI_VENDOR_IMX:
+ if (value & ESDHC_IMX_FRC_SDCLK_ON) {
+ s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
+ } else {
+ s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
+ }
+ break;
+ default:
+ break;
+ }
break;
case SDHC_HOSTCTL:
generated by cgit v1.1 at 2025-02-06 15:59:52 +0000